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| MC68HC908LJ24 MC68HC908LK24 Data Sheet M68HC08 Microcontrollers Rev. 2.1 MC68HC908LJ24/D August 16, 2005 freescale.com MC68HC908LJ24 MC68HC908LK24 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale, Inc., 2005 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet 3 Revision History Revision History Date 8/2003 Revision Level 2 First general release. Description Page Number(s) -- Data Sheet 4 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 37 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 67 Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 69 Section 5. Configuration Registers (CONFIG) . . . . . . . . 79 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 85 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . 103 Section 8. Clock Generator Module (CGM) . . . . . . . . . . 109 Section 9. System Integration Module (SIM) . . . . . . . . 139 Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 163 Section 11. Timer Interface Module (TIM) . . . . . . . . . . . 193 Section 12. Real Time Clock (RTC) . . . . . . . . . . . . . . . . 217 Section 13. Infrared Serial Communications Interface Module (IRSCI) . . . . . . . . . . . . 245 Section 14. Serial Peripheral Interface Module (SPI) . . 287 Section 15. Multi-Master IIC Interface (MMIIC) . . . . . . . 319 Section 16. Analog-to-Digital Converter (ADC) . . . . . . 333 Section 17. Liquid Crystal Display (LCD) Driver . . . . . 349 Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 375 Section 19. External Interrupt (IRQ) . . . . . . . . . . . . . . . 401 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Sections Data Sheet 5 List of Sections Section 20. Keyboard Interrupt Module (KBI). . . . . . . . 407 Section 21. Computer Operating Properly (COP) . . . . 415 Section 22. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 421 Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . . 427 Section 24. Electrical Specifications. . . . . . . . . . . . . . . 435 Section 25. Mechanical Specifications . . . . . . . . . . . . . 451 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 457 Appendix A. MC68HC908LK24. . . . . . . . . . . . . . . . . . . . 459 Data Sheet 6 List of Sections MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 1.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 1.6.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 44 1.6.2 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . .44 1.6.3 LCD Bias Voltage (VLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.4 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 45 1.6.5 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.6 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 45 1.6.8 ADC Voltage High Reference Pin (VREFH). . . . . . . . . . . . . . 45 1.6.9 ADC Voltage Low Reference Pin (VREFL) . . . . . . . . . . . . . . 46 1.6.10 Port A Input/Output (I/O) Pins (PTA7-PTA0) . . . . . . . . . . . . 46 1.6.11 Port B I/O Pins (PTB7-PTB0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.12 Port C I/O Pins (PTC7-PTC0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.13 Port D I/O Pins (PTD7-PTD0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.14 Port E I/O Pins (PTE7-PTE0) . . . . . . . . . . . . . . . . . . . . . . . 47 1.6.15 Port F I/O Pins (PTF7-PTF0). . . . . . . . . . . . . . . . . . . . . . . . 47 1.6.16 LCD Backplane and Frontplane (BP0-BP2, BP3/FP0, FP1-FP10, FP27-FP32) . . . . . . . 47 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 7 Table of Contents Section 2. Memory Map 2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 49 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Section 3. Random-Access Memory (RAM) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 4. FLASH Memory (FLASH) 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 72 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 73 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 77 Section 5. Configuration Registers (CONFIG) 5.1 5.2 5.3 5.4 5.5 Data Sheet 8 Table of Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 81 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 82 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Section 6. Central Processor Unit (CPU) 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Section 7. Oscillator (OSC) 7.1 7.2 7.3 7.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 106 7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 106 7.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 106 7.5.4 Internal RC Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.5.5 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . 106 7.5.6 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . 106 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 9 Table of Contents 7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 107 Section 8. Clock Generator Module (CGM) 8.1 8.2 8.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . 114 8.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . 116 8.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . 116 8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . 122 8.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 122 8.4.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 123 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 124 8.5.2 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . 124 8.5.3 PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . 124 8.5.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . . 124 8.5.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . 124 8.5.6 CGM VCO Clock Output (CGMVCLK) . . . . . . . . . . . . . . . . 125 8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 125 8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 125 8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .128 8.6.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . 130 8.6.4 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .131 8.6.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 132 Data Sheet 10 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 134 8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135 8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .135 8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135 8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Section 9. System Integration Module (SIM) 9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 142 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . . 143 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 144 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 144 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 145 9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 147 9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 148 9.4.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . . 148 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 149 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 149 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 149 9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 11 Table of Contents 9.6.1.3 9.6.1.4 9.6.1.5 9.6.1.6 9.6.2 9.6.3 9.6.4 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .153 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 153 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 155 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 155 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 156 9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 161 9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 162 Section 10. Monitor ROM (MON) 10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.4.3 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 10.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10.6 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10.6.1 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10.6.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 10.6.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 10.6.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 10.6.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.6.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.6.7 EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10.6.8 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Data Sheet 12 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Section 11. Timer Interface Module (TIM) 11.1 11.2 11.3 11.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 200 11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .201 11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 201 11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 202 11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 203 11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK) . 207 11.9.2 TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1, PTB4/T2CH0, PTB5/T2CH1) . . . . . . . . . . . . . . . . . . . . 207 11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 208 11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 211 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 212 11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 13 Table of Contents Section 12. Real Time Clock (RTC) 12.1 12.2 12.3 12.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 12.5.1 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 12.5.2 Calendar Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 12.5.3 Alarm Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.4 Chronograph Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.5 Timebase Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.7 RTC Clock Calibration and Compensation . . . . . . . . . . . . . . . 225 12.7.1 Calibration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.8 RTC Register and Bit Write Protection . . . . . . . . . . . . . . . . . . 227 12.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 12.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 12.10 RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.10.1 RTC Calibration Control Register (RTCCOMR) . . . . . . . . . 231 12.10.2 RTC Calibration Data Register (RTCCDAT) . . . . . . . . . . . 233 12.10.3 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . . 234 12.10.4 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . . 235 12.10.5 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . . 237 12.10.6 Alarm Minute and Hour Registers (ALMR and ALHR) . . . . 240 12.10.7 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.10.8 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.10.9 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.10.10 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.10.11 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . .243 12.10.12 Year Register (YRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.10.13 Day-Of-Week Register (DOWR) . . . . . . . . . . . . . . . . . . . . 244 12.10.14 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . 244 Data Sheet 14 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Section 13. Infrared Serial Communications Interface Module (IRSCI) 13.1 13.2 13.3 13.4 13.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6 Infrared Functional Description. . . . . . . . . . . . . . . . . . . . . . . . 250 13.6.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.6.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.7 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .252 13.7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.7.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 13.7.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.7.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.7.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.7.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.7.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .257 13.7.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.7.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.7.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.7.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.7.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 13.7.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13.7.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13.7.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13.7.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 13.9 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .267 13.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.1 PTB0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . 267 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 15 Table of Contents 13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 13.11.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.11.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.11.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.11.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.11.5 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . 280 13.11.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 13.11.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .282 13.11.8 SCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . . . . 285 Section 14. Serial Peripheral Interface Module (SPI) 14.1 14.2 14.3 14.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Pin Name Conventions and I/O Register Addresses . . . . . . . 289 14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 14.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 14.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . 293 14.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 294 14.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 296 14.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 297 14.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 14.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 14.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 Data Sheet 16 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents 14.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 309 14.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 309 14.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 314 14.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Section 15. Multi-Master IIC Interface (MMIIC) 15.1 15.2 15.3 15.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 15.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . 321 15.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . 323 15.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . . 324 15.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . 326 15.5.5 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . 328 15.5.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . 329 15.6 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 330 Section 16. Analog-to-Digital Converter (ADC) 16.1 16.2 16.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 17 Table of Contents 16.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.7.1 ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 16.7.2 ADC Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 341 16.7.3 ADC Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 341 16.7.4 ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . 341 16.7.5 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . 341 16.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 16.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .342 16.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 16.8.3 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . 346 Section 17. Liquid Crystal Display (LCD) Driver 17.1 17.2 17.3 17.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Pin Name Conventions and I/O Register Addresses . . . . . . . 350 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 17.5.1 LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 17.5.2 LCD Voltages (VLCD, VLCD1, VLCD2, VLCD3) . . . . . . . . . . . 355 17.5.3 LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 17.5.4 Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . . 356 17.5.5 Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Data Sheet 18 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.7.1 BP0-BP3 (Backplane Drivers) . . . . . . . . . . . . . . . . . . . . . . 359 17.7.2 FP0-FP32 (Frontplane Drivers) . . . . . . . . . . . . . . . . . . . . . 361 17.8 Seven Segment Display Connection . . . . . . . . . . . . . . . . . . . 365 17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 17.9.1 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . 368 17.9.2 LCD Clock Register (LCDCLK) . . . . . . . . . . . . . . . . . . . . . 370 17.9.3 LCD Data Registers (LDAT1-LDAT17) . . . . . . . . . . . . . . . 372 Section 18. Input/Output (I/O) Ports 18.1 18.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 381 18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 18.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 383 18.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 385 18.4.3 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . . 386 18.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 18.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . 387 18.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . 388 18.5.3 Port C LED Control Register (LEDC) . . . . . . . . . . . . . . . . . 389 18.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 18.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 390 18.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 392 18.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 18.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 394 18.7.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 395 18.7.3 Port E LED Control Register (LEDE) . . . . . . . . . . . . . . . . . 396 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 19 Table of Contents 18.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . 398 18.8.3 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . . 399 Section 19. External Interrupt (IRQ) 19.1 19.2 19.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 19.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 19.5 19.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 405 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 405 Section 20. Keyboard Interrupt Module (KBI) 20.1 20.2 20.3 20.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 20.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 20.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 412 20.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 412 20.6.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 413 20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 20.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 414 Data Sheet 20 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Section 21. Computer Operating Properly (COP) 21.1 21.2 21.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 21.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 418 21.5 21.6 21.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 21.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 420 Section 22. Low-Voltage Inhibit (LVI) 22.1 22.2 22.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 22.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 22.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .424 22.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 424 22.4.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 22.5 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Data Sheet 21 Table of Contents 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 Section 23. Break Module (BRK) 23.1 23.2 23.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 23.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 430 23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .430 23.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . . 430 23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 430 23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 431 23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 432 23.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 432 23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 434 Section 24. Electrical Specifications 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Data Sheet 22 Table of Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 437 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 438 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 439 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents 24.9 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.10 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.11 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 442 24.12 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 443 24.13 3.3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .444 24.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 445 24.15 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 445 24.16 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 24.17 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 24.18 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 450 Section 25. Mechanical Specifications 25.1 25.2 25.3 25.4 25.5 25.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 64-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 452 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 453 80-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 454 80-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 455 Section 26. Ordering Information 26.1 26.2 26.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Appendix A. MC68HC908LK24 A.1 A.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Table of Contents Data Sheet 23 Table of Contents A.3 A.4 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 A.5.1 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 461 A.5.2 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 461 A.5.3 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . .462 A.5.4 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . 462 A.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Data Sheet 24 Table of Contents MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 List of Figures Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 7-1 8-1 8-2 8-3 8-4 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Title Page MC68HC908LJ24 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 41 80-Pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 42 64-pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 43 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .52 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 75 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 77 CONFIG Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 81 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 82 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 90 Oscillator Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 104 CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 113 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 126 Data Sheet 25 List of Figures Figure 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 10-1 10-2 10-3 10-4 10-5 10-6 Title Page PLL Bandwidth Control Register (PBWCR) . . . . . . . . . . . . . . 129 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . . 130 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . . 130 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . . 131 PLL Reference Divider Select Register (PMDS) . . . . . . . . . . 132 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .142 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 152 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . 153 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . 155 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . 155 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 158 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 158 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 159 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 160 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 161 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 162 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 170 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Data Sheet 26 List of Figures MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Figure 10-7 10-8 10-9 10-10 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 Title Page Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . . 176 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .177 Data Block Format for ROM-Resident Routines. . . . . . . . . . . 180 EE_WRITE FLASH Memory Usage . . . . . . . . . . . . . . . . . . . .189 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .197 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 202 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 208 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 210 TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 211 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . . 211 TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 211 TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 212 TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 212 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 216 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 216 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 216 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 216 RTC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 219 RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 RTC Clock Calibration and Compensation . . . . . . . . . . . . . . . 225 1-Hz Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 RTC Write Protect State Diagram. . . . . . . . . . . . . . . . . . . . . . 228 RTC Calibration Control Register (RTCCOMR) . . . . . . . . . . . 231 RTC Calibration Data Register (RTCCDAT). . . . . . . . . . . . . . 233 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . . . . 234 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . . . . 235 RTC Status Register (RTCSR) . . . . . . . . . . . . . . . . . . . . . . . . 237 Alarm Minute Register (ALMR). . . . . . . . . . . . . . . . . . . . . . . . 240 Alarm Hour Register (ALHR) . . . . . . . . . . . . . . . . . . . . . . . . . 240 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Data Sheet 27 List of Figures Figure 12-16 12-17 12-18 12-19 12-20 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 Title Page Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Year Register (YRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Day-Of-Week Register (DOWR). . . . . . . . . . . . . . . . . . . . . . . 244 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . . . 244 IRSCI I/O Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . 248 IRSCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Infrared Sub-Module Diagram . . . . . . . . . . . . . . . . . . . . . . . . 250 Infrared SCI Data Example. . . . . . . . . . . . . . . . . . . . . . . . . . .251 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .252 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 258 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 269 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 272 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 274 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 276 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 280 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .281 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 282 SCI Infrared Control Register (SCIRCR) . . . . . . . . . . . . . . . . 285 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .289 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .290 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 291 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 295 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 296 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 298 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 299 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .301 Data Sheet 28 List of Figures MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Figure 14-10 14-11 14-12 14-13 14-14 14-15 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 Title Page Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 302 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 305 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 312 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . 314 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 321 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 321 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 323 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 324 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 326 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 328 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 329 Data Transfer Sequences for Master/Slave Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 331 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 335 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . . 339 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 342 ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . . 344 ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . . 344 ADRH and ADRL in Left Justified Mode . . . . . . . . . . . . . . . . . 345 ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . . 345 ADC Clock Control Register (ADCLK) . . . . . . . . . . . . . . . . . . 346 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 351 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . . 354 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . . 359 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 359 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 360 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . . 361 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 362 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 363 Data Sheet List of Figures 29 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Figure Title Page 17-11 1/4 Duty LCD Frontplane Driver Waveforms (continued) . . . . 364 17-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . . 365 17-13 BP0-BP2 and FP0-FP2 Output Waveforms for 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . 366 17-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .367 17-15 "e" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . 367 17-16 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . .368 17-17 LCD Clock Register (LCDCLK). . . . . . . . . . . . . . . . . . . . . . . . 370 17-18 LCD Data Registers 1-17 (LDAT1-LDAT17) . . . . . . . . . . . . . 372 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .376 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 381 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 385 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . . . . 386 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 388 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Port C LED Control Register (LEDC) . . . . . . . . . . . . . . . . . . . 389 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 392 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 395 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Port E LED Control Register (LEDE) . . . . . . . . . . . . . . . . . . . 396 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .397 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 398 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . . . . 399 19-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 403 19-2 IRQ I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . 403 Data Sheet 30 List of Figures MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Figure Title Page 19-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 406 20-1 20-2 20-3 20-4 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .408 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . 409 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 412 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 413 21-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 21-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . 418 21-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 419 22-1 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 22-2 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .422 23-1 23-2 23-3 23-4 23-5 23-6 23-7 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 429 Break Module I/O Register Summary . . . . . . . . . . . . . . . . . . . 429 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 431 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 432 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 432 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 433 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 434 24-1 Typical Internal Oscillator Frequency . . . . . . . . . . . . . . . . . . . 442 24-2 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 24-3 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 25-1 25-2 25-3 25-4 A-1 A-2 64-Pin Low-Profile Quad Flat Pack (Case No. 840F) . . . . . . . 452 64-Pin Quad Flat Pack (Case No. 840B) . . . . . . . . . . . . . . . . 453 80-Pin Low-Profile Quad Flat Pack (Case No. 917) . . . . . . . . 454 80-Pin Quad Flat Pack (Case No. 841B) . . . . . . . . . . . . . . . . 455 MC68HC908LK24 Crystal Oscillator Connection . . . . . . . . . 460 MC68HC908LK24 Configuration Register 1 (CONFIG1) . . . 460 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Figures Data Sheet 31 List of Figures Data Sheet 32 List of Figures MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 List of Tables Table 2-1 4-1 5-1 6-1 6-2 8-1 8-3 8-2 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Tables Title Page Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 FLASH Block Protect Register to Physical Address . . . . . . . . . 78 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .128 PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . . 128 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Monitor Mode Signal Requirements and Options . . . . . . . . . . 168 Mode Differences (Vectors) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 172 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 173 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 174 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 174 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 175 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 175 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 176 Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . . 179 PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ERARNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Data Sheet 33 List of Tables Table 10-14 10-15 10-16 10-17 10-18 Title Page MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ICP_LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 214 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 14-1 14-2 14-3 14-4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Compensation Algorithm for Different Values of E . . . . . . . . . 226 Write-Protected RTC Registers and Bits . . . . . . . . . . . . . . . . 227 CALOUT Pin Output Option . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 SCI Pin Functions (Standard and Infrared). . . . . . . . . . . . . . . 268 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 271 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .284 Infrared Narrow Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . 285 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 316 15-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15-2 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 16-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 16-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 16-3 ADC Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 Data Sheet 34 List of Tables MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Tables Table 17-1 17-3 17-2 17-4 17-5 17-6 18-1 18-2 18-3 18-4 18-5 18-6 18-7 Title Page Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 LCD Bias Voltage Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Resistor Ladder Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fast Charge Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . 370 LCD Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 LCD Waveform Base Clock Selection . . . . . . . . . . . . . . . . . . 371 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .378 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 20-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 22-1 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 425 22-2 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 24-16 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 437 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 438 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 439 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 441 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 442 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 443 3.3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .444 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 445 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 445 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 450 26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor List of Tables Data Sheet 35 List of Tables Table A-1 A-2 A-3 A-4 A-5 Title Page 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 461 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 461 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 462 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 462 MC68HC908LK24 Order Numbers. . . . . . . . . . . . . . . . . . . . . 462 Data Sheet 36 List of Tables MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 1. General Description 1.1 Contents 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 1.6.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 44 1.6.2 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . .44 1.6.3 LCD Bias Voltage (VLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.4 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 45 1.6.5 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.6 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 45 1.6.8 ADC Voltage High Reference Pin (VREFH). . . . . . . . . . . . . . 45 1.6.9 ADC Voltage Low Reference Pin (VREFL) . . . . . . . . . . . . . . 46 1.6.10 Port A Input/Output (I/O) Pins (PTA7-PTA0) . . . . . . . . . . . . 46 1.6.11 Port B I/O Pins (PTB7-PTB0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.12 Port C I/O Pins (PTC7-PTC0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.13 Port D I/O Pins (PTD7-PTD0) . . . . . . . . . . . . . . . . . . . . . . . 46 1.6.14 Port E I/O Pins (PTE7-PTE0) . . . . . . . . . . . . . . . . . . . . . . . 47 1.6.15 Port F I/O Pins (PTF7-PTF0). . . . . . . . . . . . . . . . . . . . . . . . 47 1.6.16 LCD Backplane and Frontplane (BP0-BP2, BP3/FP0, FP1-FP10, FP27-FP32) . . . . . . . 47 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Data Sheet 37 General Description 1.2 Introduction The MC68HC908LJ24 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 Features Features of the MC68HC908LJ24 include the following: * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families - 8-MHz at 5V operating voltage - 4-MHz at 3.3V operating voltage * * * * * 32.768kHz crystal oscillator clock input with 32MHz internal PLL Optional continuous crystal oscillator operation in stop mode 24K-bytes user program FLASH memory with security1 feature 768 bytes of on-chip RAM Up to 48 general-purpose input/output (I/O) pins: - High current 15mA sink capability on 30 pins * Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, PWM capability on each channel, and external clock input option (T1CLK and T2CLK) Real time clock (RTC) with: - Clock, calendar, alarm, and chronograph functions - Selectable periodic interrupt requests for seconds, minutes, hours, days, 2-Hz, 4-Hz, 8-Hz, 16-Hz, and 128-Hz 1. No security feature is absolutely secure. However, Freescale strategy is to make reading or copying the FLASH difficult for unauthorized users. * Data Sheet 38 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Features - Temperature drift compensation by user software and external temperature sensor with temperature drift profile from crystal vendor * * * * * * * * * * * * Serial communications interface module (SCI) with infrared (IR) encoder/decoder Inter-IC Bus interface module (IIC) Serial peripheral interface module (SPI) IRQ external interrupt pin with integrated pullup 8-bit keyboard wakeup port with programmable pullup 4/3 backplanes and static with maximum 32/33 frontplanes liquid crystal display (LCD) driver 6-channel, 10-bit successive approximation analog-to-digital converter (ADC) Resident routines for in-circuit programming and EEPROM emulation Low-power design (fully static with stop and wait modes) Master reset pin (with integrated pullup) and power-on reset Spike filter protection for EMC performance enhancement System protection features - Optional computer operating properly (COP) reset, driven by internal RC oscillator - Low-voltage detection with optional reset or interrupt - Illegal opcode detection with reset - Illegal address detection with reset * 80-pin quad flat pack (QFP), 80-pin low-profile quad flat pack (LQFP), 64-pin quad flat pack (QFP), and 64-pin low-profile quad flat pack (LQFP) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Data Sheet 39 General Description * Specific features of the MC68HC908LJ24 in 64-pin packages are: - 40 general-purpose I/Os only - High current 15-mA sink capability on 22 pins - 4/3 backplanes and static with maximum 26 or 27 frontplanes LCD driver Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit Index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908LJ24. Data Sheet 40 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description MCU Block Diagram INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7/ADC5 PTB6/ADC4 PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD PTD7/KBI7/SDA PTD6/KBI6/SCL PTD5/KBI5/T2CLK** PTD4/KBI4/T1CLK** PTD3/SPSCK/CALOUT PTD2/MOSI PTD1/MISO PTD0/SS/CALIN CONTROL AND STATUS REGISTERS -- 128 BYTES USER FLASH -- 24,576 BYTES USER RAM -- 768 BYTES MONITOR ROM -- 959 BYTES USER FLASH VECTOR SPACE -- 48 BYTES CLOCK GENERATOR MODULE OSC1 OSC2 CGMXFC 32.768-kHz OSCILLATOR 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 PORTB PORTD DDRB DDRD 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE (WITH INFRARED ENCODER/DECODER) PHASE-LOCKED LOOP REAL TIME CLOCK MODULE * RST SYSTEM INTEGRATION MODULE EXTERNAL INTERRUPT MODULE COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE LOW-VOLTAGE INHIBIT MODULE INTER IC BUS INTERFACE MODULE PORTF DDRF * IRQ PORTA DDRA SERIAL PERIPHERAL INTERFACE MODULE PTF7 : PTF0 # FP32 : FP27 PTC7/FP26 : PTC0/FP19 # VLCD VDDA VDD VSS VREFH VREFL ADC REFERENCE * Pin contains integrated pullup device. ** Pin contains integrated pullup device if configured as KBI. High current sink pin, 15mA. # Pins available on 80-pin packages only. POWER DRIVER MODULE PORTE DDRE LIQUID CRYSTAL DISPLAY PORTC DDRC PTE7/FP18 : PTE0/FP11 FP10 : FP1 BP2 : BP0 FP0/BP3 Figure 1-1. MC68HC908LJ24 Block Diagram MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Data Sheet 41 General Description 1.5 Pin Assignments PTD4/KBI4/T1CLK PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD CGMXFC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 FP0/BP3 PTD5/KBI5/T2CLK FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 PTF7 PTF6 PTD6/KBI6/SCL PTD7/KBI7/SDA FP9 FP10 PTF5 PTF4 PTE0/FP11 PTE1/FP12 62 61 VDDA 60 OSC2 OSC1 VLCD FP32 FP31 VDD VSS BP2 BP1 BP0 NC 1 VREFL VREFH PTB7/ADC5 PTB6/ADC4 PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 FP30 FP29 PTA3/KBI3 PTA2/KBI2 PTA1/KBI1 PTA0/KBI0 FP28 FP27 PTC7/FP26 PTC6/FP25 PTC5/FP24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 20 21 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 PTD0/SS/CALIN PTF3 PTF2 PTF1 PTD2/MOSI PTE2/FP13 PTE3/FP14 PTE4/FP15 PTE5/FP16 PTE6/FP17 PTE7/FP18 PTC0/FP19 PTF0 PTC1/FP20 PTC2/FP21 PTC3/FP22 PTC4/FP23 PTD1/MISO PTD3/SPSCK/CALOUT Figure 1-2. 80-Pin QFP and LQFP Pin Assignment Data Sheet 42 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor RST IRQ General Description Pin Assignments PTD4/KBI4/T1CLK PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD CGMXFC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FP0/BP3 PTD5/KBI5/T2CLK FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 PTD6/KBI6/SCL PTD7/KBI7/SDA FP9 FP10 PTE0/FP11 PTE1/FP12 50 49 VDDA OSC2 OSC1 VDD VSS BP2 BP1 BP0 1 48 VREFL VREFH PTB7/ADC5 PTB6/ADC4 PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 PTA3/KBI3 PTA2/KBI2 PTA1/KBI1 PTA0/KBI0 PTC7/FP26 PTC6/FP25 PTC5/FP24 PTD0/SS/CALIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 47 46 Pins not available on 64-LQFP package: PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 VLCD FP32 FP31 FP30 FP29 FP28 FP27 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Internal PTF7-PTF0 pads are connected to VSS. Internal FP32-FP27 pads are unconnected. Internal VLCD pad is connected to VDD. PTD3/SPSCK/CALOUT PTD1/MISO PTD2/MOSI PTE2/FP13 PTE3/FP14 PTE4/FP15 PTE5/FP16 PTE6/FP17 PTE7/FP18 PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 Figure 1-3. 64-pin QFP and LQFP Pin Assignment MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description PTC4/FP23 RST IRQ Data Sheet 43 General Description 1.6 Pin Functions Description of pin functions are provided here. 1.6.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. VSS must be grounded for proper MCU operation. 1.6.2 Analog Power Supply Pin (VDDA) VDDA is the voltage supply for the analog parts of the MCU. Connect the VDDA pin to the same voltage potential as VDD. For maximum noise immunity, route VDDA via a separate trace and place bypass capacitors as close as possible to the package (see Figure 1-4). MCU VDD 0.1 F VSS 0.1 F VDDA C1(a) C1(b) + + C2(a) C2(b) VDD NOTE: Component values shown represent typical applications. VDD Figure 1-4. Power Supply Bypassing Data Sheet 44 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Pin Functions 1.6.3 LCD Bias Voltage (VLCD) VLCD is the bias voltage supply for the LCD driver module. Connect the VLCD pin to the same voltage potential as VDD. For maximum noise immunity, route VLCD via a separate trace and place bypass capacitors as close as possible to the package. See Section 17. Liquid Crystal Display (LCD) Driver. 1.6.4 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. The OSC1 pin contains a schmitt-trigger and a spike filter for improved EMC performance. See Section 7. Oscillator (OSC). 1.6.5 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. A Schmitt-trigger and a spike filter is associated with this pin so that the device is more robust to EMC noise. This pin also contains an internal pullup resistor. See 9.4 Reset and System Initialization. 1.6.6 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Section 19. External Interrupt (IRQ). 1.6.7 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See 8.4.9 CGM External Connections. 1.6.8 ADC Voltage High Reference Pin (VREFH) VREFH is the voltage input pin for the ADC voltage high reference. See 16.7.4 ADC Voltage Reference High Pin (VREFH). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Data Sheet 45 General Description 1.6.9 ADC Voltage Low Reference Pin (VREFL) VREFL is the voltage input pin for the ADC voltage low reference. See 16.7.5 ADC Voltage Reference Low Pin (VREFL). 1.6.10 Port A Input/Output (I/O) Pins (PTA7-PTA0) PTA7-PTA0 are special function, bidirectional port pins. See 18.3 Port A. PTA7/ADC3-PTA4/ADC0 are shared with ADC, and PTA3/KBI3-PTA0/KBI0 are shared with the KBI module. 1.6.11 Port B I/O Pins (PTB7-PTB0) PTB7-PTB0 are special function, bidirectional port pins, with high current sink capability on PTB5-PTB0. See 18.4 Port B. PTB1/RxD-PTB0/TxD are shared with the SCI module, PTB5/T2CH1-PTB4/T2CH0 are shared with the TIM2, PTB3/T1CH1-PTB2/T1CH0 are shared with the TIM1, PTB7/ADC5-PTB6/ADC4 are shared with the ADC. 1.6.12 Port C I/O Pins (PTC7-PTC0) PTC7-PTC0 are special function, bidirectional port pins, with high current sink capability. See 18.5 Port C. PTC7/FP26-PTC0/FP19 are shared with the LCD frontplane drivers. 1.6.13 Port D I/O Pins (PTD7-PTD0) PTD7-PTD0 are special function, bidirectional port pins. PTD7/KBI7/SDA-PTD6/KBI6/SCL are shared with the KBI and IIC modules. See 18.6 Port D. PTD5/KBI5/T2CLK-PTD4/KBI4/T1CLK are shared with the KBI, TIM1, and TIM2 modules. PTD3/SPSCK/CALOUT-PTD0/SS/CALIN are shared with the SPI and RTC modules. Data Sheet 46 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Pin Functions 1.6.14 Port E I/O Pins (PTE7-PTE0) PTE7-PTE0 are special function, bidirectional port pins, with high current sink capability. See 18.7 Port E. PTE7/FP18-PTE0/FP11 are shared with the LCD frontplane drivers. 1.6.15 Port F I/O Pins (PTF7-PTF0) PTF7-PTF0 are general purpose bidirectional port pins with high current sink capability. See 18.8 Port F. 1.6.16 LCD Backplane and Frontplane (BP0-BP2, BP3/FP0, FP1-FP10, FP27-FP32) BP0-BP2 are the LCD backplane driver pins and FP1- FP10 and FP27-FP32 are the frontplane driver pins. FP0/BP3 is the shared driver pin between FP0 and BP3. See Section 17. Liquid Crystal Display (LCD) Driver. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor General Description Data Sheet 47 General Description Data Sheet 48 General Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 2. Memory Map 2.1 Contents 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 49 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.2 Introduction The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * 24,576 bytes of user FLASH memory 768 bytes of random-access memory (RAM) 48 bytes of user-defined vectors 959 bytes of monitor ROM 2.3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 49 Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-2 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page $0000-$007F. Additional I/O registers have the following addresses: * * * * * * * * * * * * * * * * * $FE00; SIM break status register, SBSR $FE01; SIM reset status register, SRSR $FE03; SIM break flag control register, SBFCR $FE04; Interrupt status register 1, INT1 $FE05; Interrupt status register 2, INT2 $FE06; Interrupt status register 3, INT3 $FE07; Reserved $FE08; FLASH control register, FLCR $FE09; Reserved $FE0A; Reserved $FE0B; Reserved $FE0C; break address register high, BRKH $FE0D; break address register low, BRKL $FE0E; break status and control register, BRKSCR $FE0F; LVI status register, LVISR $FFCF; FLASH block protect register, FLBPR (FLASH register) $FFFF; COP control register, COPCTL Data registers are shown in Figure 2-2, Table 2-1 is a list of vector locations. Data Sheet 50 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section $0000 $007F $0080 $037F $0380 $8FFF $9000 $EFFF $F000 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCE $FFCF $FFD0 $FFFF I/O Registers 128 Bytes RAM 768 Bytes Unimplemented 35,968 Bytes User FLASH Memory 24,576 Bytes Unimplemented 3,072 Bytes Monitor ROM 1 512 Bytes SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) Reserved SIM Break Flag Control Register (SBFCR) Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Reserved FLASH Control Register (FLCR) Reserved Reserved Reserved Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status and Control Register (BRKSCR) LVI Status Register (LVISR) Monitor ROM 2 447 Bytes FLASH Block Protect Register (FLBPR) User Vectors 48 Bytes Figure 2-1. Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 51 Memory Map Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Bit 7 PTA7 U PTB7 U PTC7 U PTD7 U 6 PTA6 U PTB6 U PTC6 U PTD6 U DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 PTE6 U DDRE6 0 5 PTA5 U PTB5 U PTC5 U PTD5 U DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 PTE5 U DDRE5 0 4 PTA4 U PTB4 U PTC4 U PTD4 U DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4 U DDRE4 0 3 PTA3 U PTB3 U PTC3 U PTD3 U DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3 U DDRE3 0 2 PTA2 U PTB2 U PTC2 U PTD2 U DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2 U DDRE2 0 R 1 PTA1 U PTB1 U PTC1 U PTD1 U DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1 U DDRE1 0 = Reserved Bit 0 PTA0 U PTB0 U PTC0 U PTD0 U DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0 U DDRE0 0 $0001 $0002 $0003 Read: DDRA7 Data Direction Register A Write: $0004 (DDRA) Reset: 0 Read: DDRB7 Data Direction Register B Write: $0005 (DDRB) Reset: 0 Read: DDRC7 Data Direction Register C $0006 Write: (DDRC) Reset: 0 Read: DDRD7 Data Direction Register D $0007 Write: (DDRD) Reset: 0 $0008 Read: Port E Data Register Write: (PTE) Reset: PTE7 U Read: DDRE7 Data Direction Register E $0009 Write: (DDRE) Reset: 0 U = Unaffected X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 13) Data Sheet 52 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. $000A Register Name Read: Port F Data Register Write: (PTF) Reset: Bit 7 PTF7 U 6 PTF6 U DDRF6 0 0 0 LEDC6 0 LEDE6 0 LEDF6 0 R 0 ERRIE 0 R6 T6 U ENSCI 0 5 PTF5 U DDRF5 0 LEDB5 0 LEDC5 0 LEDE5 0 LEDF5 0 SPMSTR 1 OVRF 0 R5 T5 U 0 0 4 PTF4 U DDRF4 0 LEDB4 0 LEDC4 0 LEDE4 0 LEDF4 0 CPOL 0 MODF 0 R4 T4 U M 0 3 PTF3 U DDRF3 0 LEDB3 0 LEDC3 0 LEDE3 0 LEDF3 0 CPHA 1 SPTE 1 R3 T3 U WAKE 0 2 PTF2 U DDRF2 0 LEDB2 0 LEDC2 0 LEDE2 0 LEDF2 0 SPWOM 0 MODFEN 0 R2 T2 U ILTY 0 R 1 PTF1 U DDRF1 0 LEDB1 0 LEDC1 0 LEDE1 0 LEDF1 0 SPE 0 SPR1 0 R1 T1 U PEN 0 = Reserved Bit 0 PTF0 U DDRF0 0 LEDB0 0 LEDC0 0 LEDE0 0 LEDF0 0 SPTIE 0 SPR0 0 R0 T0 U PTY 0 Read: DDRF7 Data Direction Register F $000B Write: (DDRF) Reset: 0 $000C Read: Port-B LED Control Register Write: (LEDB) Reset: Read: Port-C LED Control Register Write: (LEDC) Reset: Read: Port-E LED Control Register Write: (LEDE) Reset: Read: Port-F LED Control Register Write: (LEDF) Reset: Read: SPI Control Register Write: (SPCR) Reset: Read: SPI Status and Control Register Write: (SPSCR) Reset: Read: SPI Data Register Write: (SPDR) Reset: 0 0 LEDC7 0 LEDE7 0 LEDF7 0 SPRIE 0 SPRF 0 R7 T7 U $000D $000E $000F $0010 $0011 $0012 $0013 Read: LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 U = Unaffected X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 53 Memory Map Addr. $0014 Register Name Read: SCI Control Register 2 Write: (SCC2) Reset: Read: SCI Control Register 3 Write: (SCC3) Reset: Read: SCI Status Register 1 Write: (SCS1) Reset: Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: Read: SCI Infrared Control Register Write: (SCIRCR) Reset: Keyboard Status and Read: Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset: Read: Configuration Register 2 Write: (CONFIG2) Reset: U = Unaffected Bit 7 SCTIE 0 R8 U SCTE 1 0 6 TCIE 0 T8 U TC 1 0 0 R6 T6 U 0 0 0 0 0 0 KBIE6 0 STOP_ IRCDIS 0 5 SCRIE 0 DMARE 0 SCRF 0 0 4 ILIE 0 DMATE 0 IDLE 0 0 0 R4 T4 U SCP0 0 0 0 0 0 KBIE4 0 3 TE 0 ORIE 0 OR 0 0 0 R3 T3 U R 0 CKTST 0 KEYF 0 KBIE3 0 PCEH 0 2 RE 0 NEIE 0 NF 0 0 0 R2 T2 U SCR2 0 TNP1 0 0 ACKK 0 KBIE2 0 PCEL 0 R 1 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 U SCR1 0 TNP0 0 IMASKK 0 KBIE1 0 LVISEL1 0 = Reserved Bit 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0 U SCR0 0 IREN 0 MODEK 0 KBIE0 0 LVISEL0 1 $0015 $0016 $0017 0 R7 T7 U CKS 0 R 0 0 0 KBIE7 0 PEE 0 0 R5 T5 U SCP1 0 0 0 0 0 KBIE5 0 $0018 $0019 $001A $001B $001C $001D STOP_ DIV2CLK XCLKEN 0 0 X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 13) Data Sheet 54 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. $001E Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 IRQF 0 0 0 2 0 ACK 0 SSREC 0 1 IMASK 0 STOP 0 Bit 0 MODE 0 COPD 0 $001F Read: COPRS Configuration Register 1 Write: (CONFIG1) Reset: 0 LVISTOP LVIRSTD LVIPWRD 0 0 0 One-time writable register after each reset. Reset by POR only. Read: Timer 1 Status and Control $0020 Register Write: (T1SC) Reset: $0021 Read: Timer 1 Counter Register High Write: (T1CNTH) Reset: Read: Timer 1 Counter Register Low Write: (T1CNTL) Reset: Read: Timer 1 Counter Modulo Register High Write: (T1MODH) Reset: Read: Timer 1 Counter Modulo Register Low Write: (T1MODL) Reset: TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 X TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 X TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 X 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 X 0 11 0 3 0 11 1 3 1 ELS0B 0 11 X 0 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 X R PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 X = Reserved PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 X $0022 $0023 $0024 Read: Timer 1 Channel 0 Status $0025 and Control Register Write: (T1SC0) Reset: $0026 Read: Timer 1 Channel 0 Register High Write: (T1CH0H) Reset: U = Unaffected X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 55 Memory Map Addr. $0027 Register Name Read: Timer 1 Channel 0 Register Low Write: (T1CH0L) Reset: Bit 7 Bit 7 X CH1F 0 0 Bit 15 X Bit 7 X TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 6 6 X CH1IE 0 14 X 6 X TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 5 5 X 0 0 13 X 5 X TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 4 4 X MS1A 0 12 X 4 X 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 3 3 X ELS1B 0 11 X 3 X 0 0 11 0 3 0 11 1 3 1 ELS0B 0 2 2 X ELS1A 0 10 X 2 X PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 R 1 1 X TOV1 0 9 X 1 X PS1 0 9 0 1 0 9 1 1 1 TOV0 0 = Reserved Bit 0 Bit 0 X CH1MAX 0 Bit 8 X Bit 0 X PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: $0029 Read: Timer 1 Channel 1 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 Register Low Write: (T1CH1L) Reset: $002A Read: Timer 2 Status and Control $002B Register Write: (T2SC) Reset: $002C Read: Timer 2 Counter Register High Write: (T2CNTH) Reset: Read: Timer 2 Counter Register Low Write: (T2CNTL) Reset: Read: Timer 2 Counter Modulo Register High Write: (T2MODH) Reset: Read: Timer 2 Counter Modulo Register Low Write: (T2MODL) Reset: $002D $002E $002F Read: Timer 2 Channel 0 Status $0030 and Control Register Write: (T2SC0) Reset: U = Unaffected X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 13) Data Sheet 56 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. $0031 Register Name Read: Timer 2 Channel 0 Register High Write: (T2CH0H) Reset: Read: Timer 2 Channel 0 Register Low Write: (T2CH0L) Reset: Bit 7 Bit 15 X Bit 7 X CH1F 0 0 Bit 15 X Bit 7 X PLLIE 0 AUTO 0 0 0 MUL7 0 VRS7 0 6 14 X 6 X CH1IE 0 14 X 6 X PLLF 0 LOCK 0 0 0 MUL6 1 VRS6 1 5 13 X 5 X 0 0 13 X 5 X PLLON 1 ACQ 0 0 0 MUL5 0 VRS5 0 4 12 X 4 X MS1A 0 12 X 4 X BCS 0 0 0 0 0 MUL4 0 VRS4 0 3 11 X 3 X ELS1B 0 11 X 3 X PRE1 0 0 0 MUL11 0 MUL3 0 VRS3 0 2 10 X 2 X ELS1A 0 10 X 2 X PRE0 0 0 0 MUL10 0 MUL2 0 VRS2 0 R 1 9 X 1 X TOV1 0 9 X 1 X VPR1 0 0 0 MUL9 0 MUL1 0 VRS1 0 = Reserved Bit 0 Bit 8 X Bit 0 X CH1MAX 0 Bit 8 X Bit 0 X VPR0 0 R 0 MUL8 0 MUL0 0 VRS0 0 $0032 Read: Timer 2 Channel 1 Status $0033 and Control Register Write: (T2SC1) Reset: $0034 Read: Timer 2 Channel 1 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 Register Low Write: (T2CH1L) Reset: Read: PLL Control Register Write: (PTCL) Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Multiplier Select Register High Write: (PMSH) Reset: Read: PLL Multiplier Select Register Low Write: (PMSL) Reset: Read: PLL VCO Range Select Register Write: (PMRS) Reset: U = Unaffected $0035 $0036 $0037 $0038 $0039 $003A X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 57 Memory Map Addr. $003B Register Name Read: PLL Reference Divider Select Register Write: (PMDS) Reset: Read: ADC Status and Control Register Write: (ADCSR) Reset: Read: ADC Data Register high Write: (ADRH) Reset: Read: ADC Data Register low (ADRL) Write: Reset: ADC Clock Control Read: Register Write: (ADCLK) Reset: Read: RTC Calibration Control Register Write: (RTCCOMR) Reset: Read: RTC Calibration Data Register Write: (RTCCDAT) Reset: Read: RTC Control Register 1 Write: (RTCCR1) Reset: Bit 7 0 0 COCO 0 ADx R 0 ADx R 0 ADIV2 0 0 R 0 EOVL U ALMIE 0 6 0 0 AIEN 0 ADx R 0 ADx R 0 ADIV1 0 0 R 0 0 0 CHRIE 0 0 CHRCLR 0 5 0 0 ADCO 0 ADx R 0 ADx R 0 ADIV0 0 CAL 0 E5 U DAYIE 0 CHRE 0 4 0 0 ADCH4 1 ADx R 0 ADx R 0 ADICLK 0 AUTOCAL 0 E4 U HRIE 0 RTCE 0 3 RDS3 0 ADCH3 1 ADx R 0 ADx R 0 MODE1 0 OUTF1 0 E3 U MINIE 0 TBH 0 2 RDS2 0 ADCH2 1 ADx R 0 ADx R 0 MODE0 1 OUTF0 0 E2 U SECIE 0 0 0 1 RDS1 0 ADCH1 1 ADx R 0 ADx R 0 0 0 0 1 E1 U TB1IE 0 0 0 Bit 0 RDS0 1 ADCH0 1 ADx R 0 ADx R 0 0 R 0 0 0 E0 U TB2IE 0 0 0 $003C $003D $003E $003F $0040 RTCWE1 RTCWE0 $0041 $0042 $0043 Read: COMEN RTC Control Register 2 Write: (RTCCR2) Reset: U Reset by POR only. U = Unaffected X = Indeterminate = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 13) Data Sheet 58 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. $0044 Register Name Read: RTC Status Register Write: (RTCSR) Reset: Read: Alarm Minute register Write: (ALMR) Reset: Read: Alarm Hour register Write: (ALHR) Reset: Read: Second Register Write: (SECR) Reset: Read: Minute Register Write: (MINR) Reset: Read: Hour Register Write: (HRR) Reset: Read: Day Register Write: (DAYR) Reset: Read: Month Register Write: (MTHR) Reset: Read: Year Register Write: (YRR) Reset: Read: Day-Of-Week Register Write: (DOWR) Reset: U = Unaffected Bit 7 ALMF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YR7 U 0 0 6 CHRF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YR6 U 0 0 5 DAYF 0 AM5 U 0 0 SEC5 U MIN5 U 0 0 0 0 0 0 YR5 U 0 0 4 HRF 0 AM4 U AH4 U SEC4 U MIN4 U HR4 U DAY4 U 0 0 YR4 U 0 0 3 MINF 0 AM3 U AH3 U SEC3 U MIN3 U HR3 U DAY3 U MTH3 U YR3 U 0 0 2 SECF 0 AM2 U AH2 U SEC2 U MIN2 U HR2 U DAY2 U MTH2 U YR2 U DOW2 U R 1 TB1F 0 AM1 U AH1 U SEC1 U MIN1 U HR1 U DAY1 U MTH1 U YR1 U DOW1 U = Reserved Bit 0 TB2F 0 AM0 U AH0 U SEC0 U MIN0 U HR0 U DAY0 U MTH0 U YR0 U DOW0 U $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 59 Memory Map Addr. $004E Register Name Read: Chronograph Data Register Write: (CHRR) Reset: Read: LCD Clock Register Write: (LCDCLK) Reset: Read: Reserved Write: Reset: Read: LCD Control Register Write: (LCDCR) Reset: Read: LCD Data Register 1 Write: (LDAT1) Reset: Read: LCD Data Register 2 Write: (LDAT2) Reset: Read: LCD Data Register 3 Write: (LDAT3) Reset: Read: LCD Data Register 4 Write: (LDAT4) Reset: Read: LCD Data Register 5 Write: (LDAT5) Reset: Read: LCD Data Register 6 Write: (LDAT6) Reset: U = Unaffected Bit 7 0 0 0 0 R 6 CHR6 0 FCCTL1 0 R 5 CHR5 0 FCCTL0 0 R 4 CHR4 0 DUTY1 0 R 3 CHR3 0 DUTY0 0 R 2 CHR2 0 LCLK2 0 R 1 CHR1 0 LCLK1 0 R Bit 0 CHR0 0 LCLK0 0 R $004F $0050 $0051 LCDE 0 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U 0 0 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U FC 0 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U LC 0 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U LCCON3 0 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U LCCON2 0 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U R LCCON1 0 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U = Reserved LCCON0 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U $0052 $0053 $0054 $0055 $0056 $0057 X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 13) Data Sheet 60 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. $0058 Register Name Read: LCD Data Register 7 Write: (LDAT7) Reset: Read: LCD Data Register 8 Write: (LDAT8) Reset: Read: LCD Data Register 9 Write: (LDAT9) Reset: Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset: Read: LCD Data Register 14 Write: (LDAT14) Reset: Read: LCD Data Register 15 Write: (LDAT15) Reset: Read: LCD Data Register 16 Write: (LDAT16) Reset: U = Unaffected Bit 7 F13B3 U F15B3 U F17B3 U F19B3 U F21B3 U F23B3 U F25B3 U F27B3 U F29B3 U F31B3 U 6 F13B2 U F15B2 U F17B2 U F19B2 U F21B2 U F23B2 U F25B2 U F27B2 U F29B2 U F31B2 U 5 F13B1 U F15B1 U F17B1 U F19B1 U F21B1 U F23B1 U F25B1 U F27B1 U F29B1 U F31B1 U 4 F13B0 U F15B0 U F17B0 U F19B0 U F21B0 U F23B0 U F25B0 U F27B0 U F29B0 U F31B0 U 3 F12B3 U F14B3 U F16B3 U F18B3 U F20B3 U F22B3 U F24B3 U F26B3 U F28B3 U F30B3 U 2 F12B2 U F14B2 U F16B2 U F18B2 U F20B2 U F22B2 U F24B2 U F26B2 U F28B2 U F30B2 U R 1 F12B1 U F14B1 U F16B1 U F18B1 U F20B1 U F22B1 U F24B1 U F26B1 U F28B1 U F30B1 U = Reserved Bit 0 F12B0 U F14B0 U F16B0 U F18B0 U F20B0 U F22B0 U F24B0 U F26B0 U F28B0 U F30B0 U $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 61 Memory Map Addr. $0062 Register Name Read: LCD Data Register 17 Write: (LDAT17) Reset: Read: Unimplemented Write: Reset: Bit 7 6 5 4 3 F32B3 U 2 F32B2 U 1 F32B1 U Bit 0 F32B0 U $0063 to $0069 $006A Read: MMALIF MMNAKIF MMIIC Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 Read: MMAD7 MMIIC Address Register Write: (MMADR) Reset: 1 Read: MMIIC Control Register Write: (MMCR) Reset: MMEN 0 MMAD6 0 MMIEN 0 0 0 MMTD6 1 MMRD6 0 R MMBB 0 MMAD5 1 0 0 MMAST 0 MMAD4 0 0 0 MMRW 0 MMAD3 0 MMBR2 0 MMAD2 0 MMBR1 0 MMBR0 0 $006B MMAD1 MMEXTAD 0 0 0 0 0 0 $006C MMTXAK REPSEN 0 0 0 0 MMTD2 1 MMRD2 0 R $006D Read: MMRXIF MMIIC Status Register Write: 0 (MMSR) Reset: 0 Read: MMIIC Data Transmit MMTD7 Register Write: (MMDTR) Reset: 1 Read: MMRD7 MMIIC Data Receive Register Write: (MMDRR) Reset: 0 Read: Reserved Write: Reset: U = Unaffected R MMTXIF MMATCH MMSRW MMRXAK 0 MMTD5 1 MMRD5 0 R 0 MMTD4 1 MMRD4 0 R 1 MMTD3 1 MMRD3 0 R MMTXBE MMRXBF 1 MMTD1 1 MMRD1 0 R 0 MMTD0 1 MMRD0 0 R $006E $006F $0070 to $007F X = Indeterminate = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 13) Data Sheet 62 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Addr. Register Name Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR: Read: $FE02 Reserved Write: Reset: $FE03 Read: SIM Break Flag Control Register Write: (SBFCR) Reset: POR 1 R PIN 0 R COP 0 R ILOP 0 R ILAD 0 R 0 0 R LVI 0 R 0 0 R BCFE 0 IF6 R 0 IF14 R 0 0 R 0 R R R R R R R R Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: $FE08 Read: FLASH Control Register Write: (FLCR) Reset: U = Unaffected IF5 R 0 IF13 R 0 0 R 0 R IF4 R 0 IF12 R 0 0 R 0 R IF3 R 0 IF11 R 0 0 R 0 R IF2 R 0 IF10 R 0 IF18 R 0 R IF1 R 0 IF9 R 0 IF17 R 0 R 0 R 0 IF8 R 0 IF16 R 0 R 0 R 0 IF7 R 0 IF15 R 0 R 0 0 0 0 0 0 0 0 HVEN 0 MASS 0 R ERASE 0 = Reserved PGM 0 X = Indeterminate = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 13) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 63 Memory Map Addr. $FE09 Register Name Read: Reserved Write: Reset: Read: Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R $FE0A Reserved Write: Reset: Read: R R R R R R R R $FE0B Reserved Write: Reset: Read: Break Address Register High Write: (BRKH) Reset: Read: Break Address Register Low Write: (BRKL) Reset: R R R R R R R R $FE0C Bit 15 0 Bit 7 0 BRKE 0 14 0 6 0 BRKA 0 LVIIE 0 BPR6 13 0 5 0 0 0 LVIIF 0 BPR5 12 0 4 0 0 0 0 LVIIACK 0 BPR4 11 0 3 0 0 0 0 0 BPR3 10 0 2 0 0 0 0 0 BPR2 9 0 1 0 0 0 0 0 BPR1 Bit 8 0 Bit 0 0 0 0 0 0 BPR0 $FE0D Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Read: LVIOUT Low-Voltage Inhibit Status Register Write: $FE0F (LVISR) Reset: 0 $FFCF Read: FLASH Block Protect Register Write: (FLBPR)# Reset: Read: COP Control Register Write: (COPCTL) Reset: U = Unaffected BPR7 Unaffected by reset; $FF when blank Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset X = Indeterminate = Unimplemented R = Reserved # Non-volatile FLASH register; write by programming. $FFFF Figure 2-2. Control, Status, and Data Registers (Sheet 13 of 13) Data Sheet 64 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Input/Output (I/O) Section Table 2-1. Vector Addresses Priority Lowest INT Flag IF18 IF17 IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector Real Time Clock ADC Conversion Complete Keyboard MMIIC SCI Transmit SCI Receive SCI Error SPI Receive SPI Transmit TIM2 Overflow TIM2 Channel 1 TIM2 Channel 0 TIM1 Overflow TIM1 Channel 1 TIM1 Channel 0 PLL LVI IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) . Highest MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Memory Map Data Sheet 65 Memory Map Data Sheet 66 Memory Map MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.2 Introduction This section describes the 768 bytes of RAM (random-access memory). 3.3 Functional Description Addresses $0080 through $037F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64K-byte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Random-Access Memory (RAM) Data Sheet 67 Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 68 Random-Access Memory (RAM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 4. FLASH Memory (FLASH) 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 72 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 73 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 77 4.2 Introduction This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) Data Sheet 69 FLASH Memory (FLASH) Addr. $FE08 Register Name Read: FLASH Control Register Write: (FLCR) Reset: Read: FLASH Block Protect Register Write: (FLBPR)# Reset: Bit 7 0 0 BPR7 6 0 0 BPR6 5 0 0 BPR5 4 0 0 BPR4 3 HVEN 0 BPR3 2 MASS 0 BPR2 1 ERASE 0 BPR1 Bit 0 PGM 0 BPR0 $FFCF Unaffected by reset; $FF when blank = Unimplemented # Non-volatile FLASH register; write by programming. Figure 4-1. FLASH I/O Register Summary 4.3 Functional Description The FLASH memory consists of an array of 24,576 bytes for user memory plus a block of 48 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is defined as 128 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are: * * $9000-$EFFF; user memory, 24,576 bytes $FFD0-$FFFF; user interrupt vectors, 48 bytes Programming tools are available from Freescale. Contact your local Freescale representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.1 1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 70 FLASH Memory (FLASH) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) FLASH Control Register 4.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: $FE08 Bit 7 Read: Write: Reset: 0 0 0 0 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0 Figure 4-2. FLASH Control Register (FLCR) HVEN -- High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or block erase operation when the ERASE bit is set. 1 = Mass Erase operation selected 0 = Block Erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) Data Sheet 71 FLASH Memory (FLASH) 4.5 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. The 48-byte user interrupt vectors area also forms a page. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the page address range desired. 4. Wait for a time, tnvs (min. 10s). 5. Set the HVEN bit. 6. Wait for a time, terase (1ms). 7. Clear the ERASE bit. 8. Wait for a time, tnvh (5s). 9. Clear the HVEN bit. 10. After time, trcv (1s), the memory can be accessed in read mode again. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Data Sheet 72 FLASH Memory (FLASH) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) FLASH Mass Erase Operation 4.6 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the FLASH memory address range. 4. Wait for a time, tnvs (10s). 5. Set the HVEN bit. 6. Wait for a time tmerase (4ms). 7. Clear the ERASE bit. 8. Wait for a time, tnvh1 (100s). 9. Clear the HVEN bit. 10. After time, trcv (1s), the memory can be accessed again in read mode. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) Data Sheet 73 FLASH Memory (FLASH) 4.7 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxC0. Use the following procedure to program a row of FLASH memory. (Figure 4-3 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the row address range desired. 4. Wait for a time, tnvs (10s). 5. Set the HVEN bit. 6. Wait for a time, tpgs (5s). 7. Write data to the FLASH address to be programmed. 8. Wait for time, tprog (30s). 9. Repeat steps 7 and 8 until all bytes within the row are programmed. 10. Clear the PGM bit. 11. Wait for time, tnvh (5s). 12. Clear the HVEN bit. 13. After time, trcv (1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 7 to step 10), must not exceed the maximum programming time, tprog max. Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908LJ24/LK24 -- Rev. 2.1 FLASH Memory (FLASH) Freescale Semiconductor NOTE: Data Sheet 74 FLASH Memory (FLASH) FLASH Program Operation 1 Set PGM bit Algorithm for programming a row (64 bytes) of FLASH memory 2 Read the FLASH block protect register Write any data to any FLASH location within the address range of the row to be programmed Wait for a time, tnvs 3 4 5 Set HVEN bit 6 Wait for a time, tpgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, tprog Completed programming this row? N 10 Y NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tprog max. This row program algorithm assumes the row/s to be programmed are initially erased. Clear PGM bit 11 Wait for a time, tnvh 12 Clear HVEN bit 13 Wait for a time, trcv End of programming Figure 4-3. FLASH Programming Flowchart MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) Data Sheet 75 FLASH Memory (FLASH) 4.8 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations. NOTE: The 48 bytes of user interrupt vectors are always protected, regardless of the value in the FLASH block protect register. A mass erase is required to erase the vectors. When the FLBPR is program with $20, the entire memory is protected from being programmed and erased. When the FLBPR is erased ($FF), the entire memory is accessible for program and erase. Once the FLBPR is programmed with a value other than $FF, the FLBPR itself is protected. It can only be erased using a mass erase operation. NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit Data Sheet 76 FLASH Memory (FLASH) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) FLASH Block Protection 4.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Address: $FFCF Bit 7 Read: Write: Reset: BPR7 6 BPR6 5 BPR5 4 BPR4 3 BPR3 2 BPR2 1 BPR1 Bit 0 BPR0 Unaffected by reset; $FF when blank Non-volatile FLASH register; write by programming. Figure 4-4. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Block Protect Bits BPR[7:0] represent bits [14:7] of a 16-bit memory address. Bits [15:14] are logic 1's and bits [6:0] are logic 0's. 16-bit memory address Start address of FLASH block protect 1 BPR[7:0] 0000000 The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be $XX00 or $XX80 (at page boundaries -- 128 bytes) within the FLASH memory. Examples of protect start address is shown in Table 4-1: MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor FLASH Memory (FLASH) Data Sheet 77 FLASH Memory (FLASH) Table 4-1. FLASH Block Protect Register to Physical Address BPR[7:0] $00 to $1F $20 $21 $22 $23 $24 and so on... $DE $DF $E0 to $FF $EF00 (1110 1111 0000 0000) $EF80 (1110 1111 1000 0000) The entire FLASH memory is NOT protected.(2) Start Address of Protection Range(1) The entire FLASH memory is NOT protected.(2) $9000 (1001 0000 0000 0000) The entire FLASH memory is protected. $9080 (1001 0000 1000 0000) $9100 (1001 0001 0000 0000) $9180 (1001 0001 1000 0000) $9200 (1001 0010 0000 0000) Notes: 1. The end address of the protected range is always $FFFF. 2. Except the 48-byte user vectors, which is always protected. Data Sheet 78 FLASH Memory (FLASH) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 5. Configuration Registers (CONFIG) 5.1 Contents 5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 81 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 82 5.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: * * * * * * * * * * * Computer operating properly module (COP) COP timeout period (218 - 24 or 213 - 24 ICLK cycles) Low-voltage inhibit (LVI) module power LVI module reset LVI module in stop mode LVI module voltage trip point selection STOP instruction Stop mode recovery time (32 ICLK cycles or 4096 ICLK cycles) Oscillator during stop mode LCD frontplanes FP19-FP26 on port C LCD frontplanes FP11-FP18 on port E MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Configuration Registers (CONFIG) Data Sheet 79 Configuration Registers (CONFIG) Addr. $001D Register Name Read: Configuration Register 2 Write: (CONFIG2) Reset: Bit 7 PEE 0 6 STOP_ IRCDIS 0 5 4 3 PCEH 0 0 0 2 PCEL 0 SSREC 0 1 LVISEL1 0 STOP 0 Bit 0 LVISEL0 1 COPD 0 STOP_ DIV2CLK XCLKEN 0 0 $001F Read: COPRS Configuration Register 1 Write: (CONFIG1) Reset: 0 LVISTOP LVIRSTD LVIPWRD 0 0 0 One-time writable register after each reset. Reset by POR only. = Unimplemented Figure 5-1. CONFIG Registers Summary 5.3 Functional Description The configuration registers are used in the initialization of various options. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime. NOTE: The CONFIG registers are one-time writable by the user after each reset. These registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-2 and Figure 5-3. Although the LVISEL[1:0] bits default to predetermined setting of LVISEL[1:0] = 0:1 by a POR only, these bits can still be written once after each reset other than POR. Data Sheet 80 Configuration Registers (CONFIG) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Configuration Registers (CONFIG) Configuration Register 1 (CONFIG1) 5.4 Configuration Register 1 (CONFIG1) The CONFIG1 register can be written once after each reset. Address: $001F Bit 7 Read: Write: Reset: COPRS 0 6 5 4 3 0 2 SSREC 0 1 STOP 0 Bit 0 COPD 0 LVISTOP LVIRSTD LVIPWRD 0 0 0 0 Reset by POR only. = Unimplemented Figure 5-2. Configuration Register 1 (CONFIG1) COPRS -- COP Rate Select COPRS selects the COP time-out period. Reset clears COPRS. (See Section 21. Computer Operating Properly (COP).) 1 = COP time out period = 213 - 24 ICLK cycles 0 = COP time out period = 218 - 24 ICLK cycles LVISTOP -- LVI Enable in Stop Mode When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See Section 22. Low-Voltage Inhibit (LVI).) 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD -- LVI Reset Disable LVIRSTD disables the reset signal from the LVI module. (See Section 22. Low-Voltage Inhibit (LVI).) 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module. (See Section 22. Low-Voltage Inhibit (LVI).) 1 = LVI module power disabled 0 = LVI module power enabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Configuration Registers (CONFIG) Data Sheet 81 Configuration Registers (CONFIG) SSREC -- Short Stop Recovery SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay. 1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles NOTE: NOTE: Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal oscillator, do not set the SSREC bit. When the LVISTOP is enabled, the system stabilization time for power on reset and long stop recovery (both 4096 ICLK cycles) gives a delay longer than the enable time for the LVI. There is no period where the MCU is not protected from a low power condition. However, when using the short stop recovery configuration option, the 32 ICLK delay is less than the LVI's turn-on time and there exists a period in start-up where the LVI is not protecting the MCU. STOP -- STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 21. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled 5.5 Configuration Register 2 (CONFIG2) The CONFIG2 register can be written once after each reset. Address: $001D Bit 7 Read: Write: Reset: PEE 0 6 STOP_ IRCDIS 0 5 4 3 PCEH 0 2 PCEL 0 1 LVISEL1 0 Bit 0 LVISEL0 1 STOP_ DIV2CLK XCLKEN 0 0 Reset by POR only. Figure 5-3. Configuration Register 2 (CONFIG2) Data Sheet 82 Configuration Registers (CONFIG) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Configuration Registers (CONFIG) Configuration Register 2 (CONFIG2) PEE -- Port E Enable Setting PEE configures the PTE0/FP11-PTE7/FP18 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTE0/FP11-PTE7/FP18 pins configured as LCD frontplane driver pins: FP11-FP18 0 = PTE0/FP11-PTE7/FP18 pins configured as standard I/O pins: PTE0-PTE7 STOP_IRCDIS -- Internal RC Oscillator Stop Mode Disable Setting STOP_IRCDIS disables the internal RC oscillator during stop mode. When this bit is cleared, the internal RC oscillator continues to operate in stop mode. Reset clears this bit. 1 = Internal RC oscillator disabled during stop mode 0 = Internal RC oscillator enabled during stop mode STOP_XCLKEN -- Crystal Oscillator Stop Mode Enable Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator to continue operating in stop mode. This is useful for driving the real time clock module to allow it to generate periodic wake up while in stop mode. When this bit is cleared, the external XTAL oscillator will be disabled during stop mode. Reset clears this bit. 1 = XTAL oscillator enabled during stop mode 0 = XTAL oscillator disabled during stop mode DIV2CLK -- Divide-by-2 Clock Bypass When CGMXCLK is selected to drive the system clocks (BCS=0), setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2 divider in the CGM module; CGMOUT will equal CGMXCLK and bus clock will equal CGMXCLK divide-by-2. DIV2CLK bit has no effect when the BCS=1 in the PLL control register (CGMVCLK selected and divide-by-2 always enabled). Reset clears this bit. 1 = Divide-by-2 divider bypassed; When BSC=0, CGMOUT equals CGMXCLK 0 = Divide-by-2 divider enabled; When BSC=0, CGMOUT equals CGMXCLK divide-by-2 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Configuration Registers (CONFIG) Data Sheet 83 Configuration Registers (CONFIG) PCEH -- Port C Enable High Nibble Setting PCEH configures the PTC4/FP23-PTC7/FP26 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTC4/FP23-PTC7/FP26 pins configured as LCD frontplane driver pins: FP23-FP26 0 = PTC4/FP23-PTC7/FP26 pins configured as standard I/O pins: PTC4-PTC7 PCEL -- Port C Enable Low Nibble Setting PCEL configures the PTC0/FP19-PTC3/FP22 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTC0/FP19-PTC3/FP22 pins configured as LCD frontplane driver pins: FP19-FP22 0 = PTC0/FP19-PTC3/FP22 pins configured as standard I/O pins: PTC0-PTC3 LVISEL[1:0] -- LVI Operating Mode Selection LVISEL[1:0] selects the voltage operating mode of the LVI module. (See Section 22. Low-Voltage Inhibit (LVI).) The voltage mode selected for the LVI should match the operating VDD. See Section 24. Electrical Specifications for the LVI voltage trip points for each of the modes. Table 5-1. LVI Trip Point Selection LVISEL1 0 0 1 1 LVISEL0 0 1 0 1 Operating Mode Reserved 3.3V(1) 5V Reserved Notes: 1. Default setting after a power-on-reset. Data Sheet 84 Configuration Registers (CONFIG) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 85 Central Processor Unit (CPU) 6.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 6.3 Features Feature of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-Bit index register with X-register manipulation instructions 8-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes Low-power stop and wait modes Data Sheet 86 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) CPU Registers 6.4 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0 Figure 6-2. Accumulator (A) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 87 Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 X = Indeterminate Figure 6-3. Index Register (H:X) 6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Figure 6-4. Stack Pointer (SP) Data Sheet 88 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) CPU Registers NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Figure 6-5. Program Counter (PC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 89 Central Processor Unit (CPU) 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Bit 7 Read: Write: Reset: 6 1 1 5 1 1 4 H X 3 I 1 2 N X 1 Z X Bit 0 C X V X X = Indeterminate Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 Data Sheet 90 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) CPU Registers I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 91 Central Processor Unit (CPU) C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock. * Data Sheet 92 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) CPU During Break Interrupts 6.6.2 Stop Mode The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock. * After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 6.7 CPU During Break Interrupts If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. (See Section 23. Break Module (BRK).) The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 6.8 Instruction Set Summary Table 6-1 provides a summary of the M68HC08 instruction set. 6.9 Opcode Map The opcode map is provided in Table 6-2. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 93 Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Sheet 1 of 8) Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operand ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd Address Mode Opcode A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F Effect on CCR VHINZC Operation Description Add with Carry A (A) + (M) + (C) - IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2 Add without Carry A (A) + (M) - Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X SP (SP) + (16 M) H:X (H:X) + (16 M) - - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 Logical AND A (A) & (M) 0-- Arithmetic Shift Left (Same as LSL) C b7 b0 0 -- Arithmetic Shift Right b7 b0 C -- Branch if Carry Bit Clear PC (PC) + 2 + rel ? (C) = 0 - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7) BCLR n, opr Clear Bit n in M Mn 0 Data Sheet 94 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Opcode Map Table 6-1. Instruction Set Summary (Sheet 2 of 8) Cycles 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 Source Form BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operand rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr Address Mode Opcode 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 Effect on CCR VHINZC Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0 Operation Description - - - - - - REL - - - - - - REL - - - - - - REL PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 - IX1 IX SP1 SP2 Bit Test (A) & (M) 0-- Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 95 Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Sheet 3 of 8) Cycles 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 dd 3 1 1 1 3 2 4 Source Form Operand dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr ff ff Address Mode Opcode 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F Effect on CCR VHINZC Operation Description BRCLR n,opr,rel Branch if Bit n in M Clear PC (PC) + 3 + rel ? (Mn) = 0 ----- DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never PC (PC) + 2 - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRSET n,opr,rel Branch if Bit n in M Set PC (PC) + 3 + rel ? (Mn) = 1 ----- BSET n,opr Set Bit n in M Mn 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel - - - - - - REL CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask DIR PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (X) - (M) = $00 ------ IX1+ PC (PC) + 3 + rel ? (A) - (M) = $00 IX+ PC (PC) + 2 + rel ? (A) - (M) = $00 SP1 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 Clear Data Sheet 96 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Opcode Map Table 6-1. Instruction Set Summary (Sheet 4 of 8) Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 dd rr rr rr ff rr rr ff rr dd 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Operand ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff ff ff Address Mode Opcode A1 B1 C1 D1 E1 F1 9EE1 9ED1 33 43 53 63 73 9E63 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Effect on CCR VHINZC Operation Description Compare A with M (A) - (M) -- IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP1 SP2 INH Complement (One's Complement) M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1) 0-- Compare H:X with M -- Compare X with M (X) - (M) -- Decimal Adjust A (A)10 A (A) - 1 or M (M) - 1 or X (X) - 1 U-- DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH - - - - - - INH IX1 IX SP1 DIR INH INH - IX1 IX SP1 INH IMM DIR EXT IX2 - IX1 IX SP1 SP2 Decrement -- Divide ---- Exclusive OR M with A A (A M) 0-- MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 97 Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Sheet 5 of 8) Cycles 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 Source Form INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Operand dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff Address Mode Opcode 3C 4C 5C 6C 7C 9E6C BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE 38 48 58 68 78 9E68 34 44 54 64 74 9E64 Effect on CCR VHINZC M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1 Operation Description Increment -- DIR INH INH - IX1 IX SP1 Jump PC Jump Address DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2 - IMM DIR Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address Load A from M A (M) 0-- Load H:X from M H:X (M:M + 1) 0-- Load X from M X (M) 0-- IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 Logical Shift Left (Same as ASL) C b7 b0 0 -- Logical Shift Right 0 b7 b0 C --0 Data Sheet 98 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Opcode Map Table 6-1. Instruction Set Summary (Sheet 6 of 8) Cycles 5 4 4 4 5 dd 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 dd 4 1 1 4 3 5 4 1 1 4 3 5 1 Source Form MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operand dd dd dd ii dd dd ff ff ff ff dd ff ff Address Mode Opcode 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 49 59 69 79 9E69 36 46 56 66 76 9E66 9C Effect on CCR VHINZC (M)Destination (M)Source Move H:X (H:X) + 1 (IX+D, DIX+) Unsigned multiply X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4]) 0-- Operation Description DD DIX+ - IMD IX+D - 0 - - - 0 INH DIR INH INH IX1 IX SP1 Negate (Two's Complement) -- No Operation Nibble Swap A - - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2 Inclusive OR A and M A (A) | (M) 0-- Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X) - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 Rotate Left through Carry C b7 b0 -- Rotate Right through Carry b7 b0 C -- Reset Stack Pointer SP $FF - - - - - - INH MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 99 Central Processor Unit (CPU) Table 6-1. Instruction Set Summary (Sheet 7 of 8) Cycles 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 Source Form Operand Address Mode Opcode 80 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 Effect on CCR VHINZC SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL) Operation Description RTI Return from Interrupt INH RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Return from Subroutine - - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2 Subtract with Carry A (A) - (M) - (C) -- Set Carry Bit Set Interrupt Mask C1 I1 - - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR Store A in M M (A) 0-- Store H:X in M Enable IRQ Pin; Stop Oscillator (M:M + 1) (H:X) I 0; Stop Oscillator 0-- - - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2 Store X in M M (X) 0-- Subtract A (A) - (M) -- Data Sheet 100 Central Processor Unit (CPU) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Opcode Map Table 6-1. Instruction Set Summary (Sheet 8 of 8) Cycles 9 2 1 1 dd 3 1 1 3 2 4 2 1 2 Source Form Operand ff ff Address Mode Opcode 83 84 97 85 3D 4D 5D 6D 7D 9E6D 95 9F 94 Effect on CCR VHINZC PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR) Operation Description SWI Software Interrupt - - 1 - - - INH TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Transfer A to CCR Transfer A to X Transfer CCR to A INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1 Test for Negative or Zero (A) - $00 or (X) - $00 or (M) - $00 0-- Transfer SP to H:X Transfer X to A Transfer H:X to SP H:X (SP) + 1 A (X) (SP) (H:X) - 1 n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & | - - - - - - INH - - - - - - INH - - - - - - INH Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit () -( ) # ? : -- Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Central Processor Unit (CPU) Data Sheet 101 102 Central Processor Unit (CPU) Freescale Semiconductor Data Sheet LSB Central Processor Unit (CPU) Table 6-2. Opcode Map Bit Manipulation DIR DIR MSB Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM DIR B EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 E SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 IX F 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 0 1 2 3 4 5 6 7 8 9 A B C D E F 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH 5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX 7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR MSB LSB 3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1 2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX MC68HC908LJ24/LK24 -- Rev. 2.1 Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions INH IMM DIR EXT DD IX+D SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment 0 High Byte of Opcode in Hexadecimal Low Byte of Opcode in Hexadecimal 0 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode Data Sheet -- MC68HC908LJ24 Section 7. Oscillator (OSC) 7.1 Contents 7.2 7.3 7.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 106 7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 106 7.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 106 7.5.4 Internal RC Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.5.5 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . 106 7.5.6 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . 106 7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 107 7.2 Introduction The oscillator module provides the reference clock for the clock generator module (CGM), the real time clock module (RTC), and other MCU sub-systems. The oscillator module consist of two types of oscillator circuits: * * Internal RC oscillator 32.768kHz crystal (x-tal) oscillator MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Data Sheet 103 Oscillator (OSC) The reference clock for the CGM, real time clock module (RTC) and other MCU sub-systems is driven by the crystal oscillator. The COP module is always driven by internal RC clock. The internal RC oscillator runs continuously after a POR or reset and is always available in run and wait modes. In stop mode, it can be disabled by setting the STOP_IRCDIS bit in CONFIG2 register. Figure 7-1. shows the block diagram of the oscillator module. From SIM SIMOSCEN CONFIG2 STOP_IRCDIS EN INTERNAL RC OSCILLATOR INTERNAL RC OSCILLATOR CGMRCLK ICLK To SIM, COP To CGM PLL CONFIG2 STOP_XCLKEN CGMXCLK To RTC, ADC, LCD, CGM Clock Selection MUX MCU CRYSTAL OSCILLATOR OSC1 RB OSC2 RS* *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data. See Section 24. for component value requirements. C1 32.768kHz (typical) C2 X1 Figure 7-1. Oscillator Module Block Diagram Data Sheet 104 Oscillator (OSC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Internal Oscillator 7.3 Internal Oscillator The internal RC oscillator clock (ICLK) is a free running 64kHz clock (at VDD = 5V) that requires no external components. It is the reference clock input to the computer operating properly (COP) module. The ICLK can be turned off in stop mode by setting the STOP_IRCDIS bit in CONFIG2. After reset, the bit is clear by default and ICLK is enabled during stop mode. 7.4 X-tal Oscillator The crystal (x-tal) oscillator circuit is designed for use with an external 32.768kHz crystal or ceramic resonator to provide an accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 (32.768kHz) Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional) The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information. 7.5 I/O Signals The following paragraphs describe the oscillator I/O signals. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Data Sheet 105 Oscillator (OSC) 7.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier. Schmitt trigger and glitch filter are implemented on this pin to improve EMC performance. See Section 24. Electrical Specifications for detail specification of the glitch filter. 7.5.2 Crystal Amplifier Output Pin (OSC2) OSC2 pin is the output of the crystal oscillator inverting amplifier. 7.5.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal from the system integration module (SIM) enables/disables the x-tal oscillator circuit. 7.5.4 Internal RC Clock (ICLK) The ICLK clock is the output from the internal RC oscillator. This clock drives the SIM and COP modules. 7.5.5 CGM Oscillator Clock (CGMXCLK) The CGMXCLK clock is the output from the x-tal oscillator. This clock drives to CGM, real time clock module, analog-to-digital converter, liquid crystal display driver module, and other MCU sub-systems. 7.5.6 CGM Reference Clock (CGMRCLK) This is buffered signal of CGMXCLK, it is used by the CGM as the phase-locked-loop (PLL) reference clock. 7.6 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Data Sheet 106 Oscillator (OSC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Oscillator During Break Mode 7.6.1 Wait Mode The WAIT instruction has no effect on the oscillator module. CGMXCLK, CGMRCLK, and ICLK continues to drive the MCU modules. 7.6.2 Stop Mode The STOP instruction clears the SIMOSCEN signal, and hence the CGMXCLK (and CGMRCLK) clock stops running. For continuous CGMXCLK operation in stop mode, set the STOP_XCLKEN to logic 1 before entering stop mode. Continuous CGMXCLK operation in stop mode allows the RTC module to generate interrupts to wake up the CPU. By default, the internal RC oscillator clock, ICLK, continues to run in stop mode. To disable the ICLK in stop mode, set the STOP_IRCDIS bit to logic 1 before entering stop mode. 7.7 Oscillator During Break Mode The oscillator circuits continue to drive CGMXCLK, CGMRCLK, and ICLK when the device enters the break state. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Data Sheet 107 Oscillator (OSC) Data Sheet 108 Oscillator (OSC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . 114 8.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . 116 8.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . 116 8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . 122 8.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 122 8.4.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 123 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 124 8.5.2 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . 124 8.5.3 PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . 124 8.5.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . . 124 8.5.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . 124 8.5.6 CGM VCO Clock Output (CGMVCLK) . . . . . . . . . . . . . . . . 125 8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 125 8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 125 8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .128 8.6.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . 130 8.6.4 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .131 8.6.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 132 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 109 Clock Generator Module (CGM) 8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 134 8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135 8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .135 8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135 8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.2 Introduction This section describes the clock generator module (CGM). The CGM generates the base clock signal, CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop (PLL) clock, CGMPCLK, divided by two. CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT/2. The PLL is a frequency generator designed for use with a low frequency crystal (typically 32.768kHz) to generate a base frequency and dividing to a maximum bus frequency of 8MHz. Data Sheet 110 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Features 8.3 Features Features of the CGM include: * * * * * * * * Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low-frequency crystal operation with low-power operation and high-output frequency resolution Programmable prescaler for power-of-two increases in frequency Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Configuration register bit to allow oscillator operation during stop mode 8.4 Functional Description The CGM consists of three major sub-modules: * * Oscillator module -- The oscillator module generates the constant reference frequency clock, CGMRCLK (buffered CGMXCLK). Phase-locked loop (PLL) -- The PLL generates the programmable VCO frequency clock, CGMVCLK, and the divided, CGMPCLK. The CGMPCLK is one of the reference clocks to the base clock selector circuit. Base clock selector circuit -- This software-controlled circuit selects the one of three clocks as the base clock, CGMOUT: CGMXCLK, CGMXCLK divided by two, or CGMPCLK divided by two. * Figure 8-1 shows the structure of the CGM. Figure 8-2 is a summary of the CGM registers. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 111 Clock Generator Module (CGM) OSCILLATOR (OSC) MODULE See Section 7. Oscillator (OSC). SIMOSCEN From SIM INTERNAL RC OSC ICLK To SIM (and COP) OSC2 CRYSTAL OSCILLATOR OSC1 CGMXCLK CGMRCLK T0 RTC, ADC, LCD USER MODE: CGMOUT = B PHASE-LOCKED LOOP (PLL) RESET: A RESET: A A CGMRDV BS REFERENCE DIVIDER R RDS[3:0] VDDA CGMXFC VSSA CGMRCLK BCS CGMPCLK VPR[1:0] VRS[7:0] L 2E 1 /2 A B1 S A BS 1 CGMOUT To SIM SIMDIV2 From SIM BASE CLOCK SELECT CIRCUIT DIV2CLK CONFIG2 PHASE DETECTOR LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR PLL ANALOG LOCK DETECTOR AUTOMATIC MODE CONTROL INTERRUPT CONTROL CGMINT To SIM LOCK MUL[11:0] N CGMVDV FREQUENCY DIVIDER AUTO ACQ PLLIE PRE[1:0] 2P FREQUENCY DIVIDER PLLF CGMVCLK CGMPCLK Figure 8-1. CGM Block Diagram Data Sheet 112 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Functional Description Addr. Register Name Read: PLL Control Register Write: (PTCL) Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Multiplier Select Register High Write: (PMSH) Reset: Read: PLL Multiplier Select Register Low Write: (PMSL) Reset: Read: PLL VCO Range Select Register Write: (PMRS) Reset: Read: PLL Reference Divider Select Register Write: (PMDS) Reset: Bit 7 PLLIE 0 AUTO 0 0 6 PLLF 5 PLLON 1 ACQ 0 0 4 BCS 0 0 3 PRE1 0 0 2 PRE0 0 0 1 VPR1 0 0 Bit 0 VPR0 0 R 0 MUL8 0 MUL0 0 VRS0 0 RDS0 1 $0036 0 LOCK $0037 0 0 0 0 0 MUL11 0 MUL3 0 VRS3 0 RDS3 0 R 0 MUL10 0 MUL2 0 VRS2 0 RDS2 0 = Reserved 0 MUL9 0 MUL1 0 VRS1 0 RDS1 0 $0038 0 MUL7 0 VRS7 0 0 0 MUL6 1 VRS6 1 0 0 MUL5 0 VRS5 0 0 0 MUL4 0 VRS4 0 0 $0039 $003A $003B 0 0 0 0 = Unimplemented NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 8-2. CGM I/O Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 113 Clock Generator Module (CGM) 8.4.1 Oscillator Module The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module. CGMXCLK or CGMXCLK divide-by-two can be selected to drive the SIM module to generate the system bus clocks. CGMRCLK is the reference clock for the phase-lock-loop, to generate a higher frequency clock. The oscillator module also provides the reference clock for the real time clock (RTC) module. See Section 7. Oscillator (OSC) for detailed description on oscillator module. See Section 12. Real Time Clock (RTC) for detailed description on RTC. 8.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 8.4.3 PLL Circuits The PLL consists of these circuits: * * * * * * * Voltage-controlled oscillator (VCO) Reference divider Frequency pre-scaler Modulo VCO frequency divider Phase detector Loop filter Lock detector Data Sheet 114 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Functional Description The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or (L x 2E)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a factor, R. The divider's output is the final reference clock, CGMRDV, running at a frequency, fRDV = fRCLK/R. With an external crystal (30kHz-100kHz), always set R = 1 for specified performance. With an external high-frequency clock source, use R to divide the external frequency to between 30kHz and 100kHz. The VCO's output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a power-of-two factor P (the CGMPCLK) and the modulo divider reduces the VCO clock by a factor, N. The dividers' output is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N x 2P). (See 8.4.6 Programming the PLL for more information.) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 8.4.4 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 115 Clock Generator Module (CGM) 8.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 8.6.2 PLL Bandwidth Control Register.) Tracking mode -- In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. (See 8.4.8 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set. * 8.4.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 8.6.2 PLL Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. (See 8.4.8 Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 8.7 Interrupts for information and precautions on using interrupts.) Data Sheet 116 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Functional Description The following conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. (See 8.4.4 Acquisition and Tracking Modes.) The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 8.9 Acquisition/Lock Time Specifications for more information.) The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 8.9 Acquisition/Lock Time Specifications for more information.) CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. (See 8.6.1 PLL Control Register.) * * * * The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 117 Clock Generator Module (CGM) The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 8.9 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL). Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGM are disabled. * * * * 8.4.6 Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency, fBUSDES. 2. Calculate the desired VCO frequency, fVCLKDES. f VCLKDES = 2 x f CGMPCLK = 2 x 4 P P x fBUSDES where P is the power of two multiplier, and can be 0, 1, 2, or 3 3. Choose a practical PLL reference frequency, fRCLK, and the reference clock divider, R. Typically, the reference is 32.768kHz and R = 1. Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. Data Sheet 118 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Functional Description The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is 2N f VCLK = ----------- ( f RCLK ) R P where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Section 24. Electrical Specifications. Choose the reference divider, R = 1. When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with practical choices of fRCLK, and choose the fRCLK that gives the lowest R. f VCLKDES f VCLKDES R = round R MAX x ------------------------- - integer ------------------------- f RCLK f RCLK 4. Calculate N: R x f VCLKDES N = round ------------------------------------ P f x2 RCLK 5. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. 2N f VCLK = ----------- ( f RCLK ) R f BUS = VCLK ---------P P f 2 x4 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 119 Clock Generator Module (CGM) 6. Select the VCO's power-of-two range multiplier E, according to this table: Frequency Range 0 < fVCLK < 9,830,400 9,830,400 fVCLK < 19,660,800 19,660,800 fVCLK < 39,321,600 NOTE: Do not program E to a value of 3. E 0 1 2 7. Select a VCO linear range multiplier, L, where fNOM = 38.4kHz f VCLK L = round -------------------------- 2E x f NOM 8. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. f VRS = ( L x 2 )f NOM E For proper operation, f NOM x 2 f VRS - f VCLK -------------------------2 E 9. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application's tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK. NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. Data Sheet 120 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Functional Description 10. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. NOTE: The values for P, E, N, L, and R can only be programmed when the PLL is off (PLLON = 0). Table 8-1 provides numeric examples (numbers are in hexadecimal notation): Table 8-1. Numeric Examples CGMVCLK 8.0 MHz 9.8304 MHz 10.0 MHz 16 MHz 19.6608 MHz 20 MHz 29.4912 MHz 32 MHz 32 MHz 32 MHz 32 MHz CGMPCLK 8.0 MHz 9.8304 MHz 10.0 MHz 16 MHz 19.6608 MHz 20 MHz 29.4912 MHz 32 MHz 16 MHz 8 MHz 4 MHz fBUS 2.0 MHz 2.4576 MHz 2.5 MHz 4.0 MHz 4.9152 MHz 5.0 MHz 7.3728 MHz 8.0 MHz 4.0 MHz 2.0 MHz 1.0 MHz fRCLK 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz 32.768 kHz R 1 1 1 1 1 1 1 1 1 1 1 N F5 12C 132 1E9 258 263 384 3D1 1E9 F5 7B P 0 0 0 0 0 0 0 0 1 2 3 E 0 1 1 1 2 2 2 2 2 2 2 L D1 80 83 D1 80 82 C0 D0 D0 D0 D0 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 121 Clock Generator Module (CGM) 8.4.7 Special Programming Exceptions The programming method described in 8.4.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: * * A 0 value for R or N is interpreted exactly the same as a value of 1. A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 8.4.8 Base Clock Selector Circuit.) 8.4.8 Base Clock Selector Circuit This circuit is used to select either the oscillator clock, CGMXCLK, or the divided VCO clock, CGMPCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMPCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of CGMOUT, is one-fourth the frequency of the selected clock (CGMXCLK or CGMPCLK). For the CGMXCLK, the divide-by-2 can be by-passed by setting the DIV2CLK bit in the CONFIG2 register. Therefore, the bus clock frequency can be one-half of CGMXCLK. The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the divided VCO clock. The divided VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock. Data Sheet 122 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) I/O Signals 8.4.9 CGM External Connections In its typical configuration, the CGM requires up to four external components. Figure 8-3 shows the external components for the PLL: * * Bypass capacitor, CBYP Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 8.9 Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL performance.) MCU CGMXFC VSSA VDDA VDD 10 k 0.033 F 0.01 F CBYP 0.1 F Note: Filter network in box can be replaced with a 0.47F capacitor, but will degrade stability. Figure 8-3. CGM External Connections 8.5 I/O Signals The following paragraphs describe the CGM I/O signals. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 123 Clock Generator Module (CGM) 8.5.1 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 8-3.) NOTE: To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. 8.5.2 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.3 PLL Analog Ground Pin (VSSA) VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage potential as the VSS pin. NOTE: NOTE: Route VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. On this MCU, the VSSA is physically bonded to the VSS pin. 8.5.4 Oscillator Output Frequency Signal (CGMXCLK) CGMXCLK is the oscillator output signal. It runs at the full speed of the oscillator, and is generated directly from the crystal oscillator circuit, the RC oscillator circuit, or the internal oscillator circuit. 8.5.5 CGM Reference Clock (CGMRCLK) CGMRCLK is a buffered version of CGMXCLK, this clock is the reference clock for the phase-locked-loop circuit. Data Sheet 124 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) CGM Registers 8.5.6 CGM VCO Clock Output (CGMVCLK) CGMVCLK is the clock output from the VCO. 8.5.7 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be equal to CGMXCLK, CGMXCLK divided by two, or CGMPCLK divided by two. 8.5.8 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. 8.6 CGM Registers The following registers control and monitor operation of the CGM: * * * * * PLL control register (PCTL) (See 8.6.1 PLL Control Register.) PLL bandwidth control register (PBWC) (See 8.6.2 PLL Bandwidth Control Register.) PLL multiplier select registers (PMSH and PMSL) (See 8.6.3 PLL Multiplier Select Registers.) PLL VCO range select register (PMRS) (See 8.6.4 PLL VCO Range Select Register.) PLL reference divider select register (PMDS) (See 8.6.5 PLL Reference Divider Select Register.) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 125 Clock Generator Module (CGM) 8.6.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 5 PLLON 1 4 BCS 0 3 PRE1 0 2 PRE0 0 1 VPR1 0 Bit 0 VPR0 0 0 = Unimplemented Figure 8-4. PLL Control Register (PCTL) PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF -- PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. Data Sheet 126 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) CGM Registers PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 8.4.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base Clock Select Bit This read/write bit selects either the oscillator output, CGMXCLK, or the divided VCO clock, CGMPCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 8.4.8 Base Clock Selector Circuit.) Reset clears the BCS bit. 1 = CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMPCLK requires two writes to the PLL control register. (See 8.4.8 Base Clock Selector Circuit.) PRE1 and PRE0 -- Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See 8.4.3 PLL Circuits and 8.4.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set. Reset clears these bits. These prescaler bits affects the relationship between the VCO clock and the final system bus clock. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 127 Clock Generator Module (CGM) Table 8-2. PRE 1 and PRE0 Programming PRE1 and PRE0 00 01 10 11 P 0 1 2 3 Prescaler Multiplier 1 2 4 8 VPR1 and VPR0 -- VCO Power-of-Two Range Select Bits These read/write bits control the VCO's hardware power-of-two range multiplier E that, in conjunction with L (See 8.4.3 PLL Circuits, 8.4.6 Programming the PLL, and 8.6.4 PLL VCO Range Select Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits. Table 8-3. VPR1 and VPR0 Programming VPR1 and VPR0 00 01 10 E 0 1 2 VCO Power-of-Two Range Multiplier 1 2 4 NOTE: Do not program E to a value of 3. 8.6.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode Data Sheet 128 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) CGM Registers Address: $0037 Bit 7 6 LOCK 5 ACQ 0 4 0 3 0 2 0 1 0 Bit 0 R 0 Read: Write: Reset: AUTO 0 0 0 0 R 0 = Reserved 0 = Unimplemented Figure 8-5. PLL Bandwidth Control Register (PBWCR) AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 129 Clock Generator Module (CGM) 8.6.3 PLL Multiplier Select Registers The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider. Address: $0038 Bit 7 Read: Write: Reset: 0 0 0 0 0 6 0 5 0 4 0 3 MUL11 0 2 MUL10 0 1 MUL9 0 Bit 0 MUL8 0 = Unimplemented Figure 8-6. PLL Multiplier Select Register High (PMSH) Address: $0039 Bit 7 Read: Write: Reset: MUL7 0 6 MUL6 1 5 MUL5 0 4 MUL4 0 3 MUL3 0 2 MUL2 0 1 MUL1 0 Bit 0 MUL0 0 Figure 8-7. PLL Multiplier Select Register Low (PMSL) MUL[11:0] -- Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N. (See 8.4.3 PLL Circuits and 8.4.6 Programming the PLL.) A value of $0000 in the multiplier select registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Data Sheet 130 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) CGM Registers 8.6.4 PLL VCO Range Select Register The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: $003A Bit 7 Read: Write: Reset: VRS7 0 6 VRS6 1 5 VRS5 0 4 VRS4 0 3 VRS3 0 2 VRS2 0 1 VRS1 0 Bit 0 VRS0 0 Figure 8-8. PLL VCO Range Select Register (PMRS) VRS[7:0] -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 8.4.3 PLL Circuits, 8.4.6 Programming the PLL, and 8.6.1 PLL Control Register.), controls the hardware center-of-range frequency, fVRS. VRS[7:0] cannot be written when the PLLON bit in the PCTL is set. (See 8.4.7 Special Programming Exceptions.) A value of $00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 8.4.8 Base Clock Selector Circuit and 8.4.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64. NOTE: The VCO range select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 131 Clock Generator Module (CGM) 8.6.5 PLL Reference Divider Select Register The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: $003B Bit 7 Read: Write: Reset: 0 6 0 5 0 4 0 3 RDS3 0 2 RDS2 0 1 RDS1 0 Bit 0 RDS0 1 0 0 0 0 = Unimplemented Figure 8-9. PLL Reference Divider Select Register (PMDS) RDS[3:0] -- Reference Divider Select Bits These read/write bits control the modulo reference divider that selects the reference division factor, R. (See 8.4.3 PLL Circuits and 8.4.6 Programming the PLL.) RDS[3:0] cannot be written when the PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (See 8.4.7 Special Programming Exceptions.) Reset initializes the register to $01 for a default divide value of 1. NOTE: NOTE: The reference divider select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). The default divide value of 1 is recommended for all applications. Data Sheet 132 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Interrupts 8.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the divided VCO clock, CGMPCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. NOTE: Software can select the CGMPCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. 8.8 Special Modes The WAIT instruction puts the MCU in low power-consumption standby modes. 8.8.1 Wait Mode The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 133 Clock Generator Module (CGM) 8.8.2 Stop Mode If the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) is configured to disabled the oscillator in stop mode, then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMOUT, CGMVCLK, CGMPCLK, and CGMINT). If the STOP instruction is executed with the divided VCO clock, CGMPCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the oscillator clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. If the oscillator stop mode enable bit is configured for continuous oscillator operation in stop mode, then the phase locked loop is shut off but the CGMXCLK will continue to drive the SIM and other MCU subsystems. 8.8.3 CGM During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 9.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Data Sheet 134 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Acquisition/Lock Time Specifications 8.9 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 8.9.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0Hz to 1MHz, the acquisition time is the time taken for the frequency to reach 1MHz 50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at 1MHz and suffers a -100kHz noise hit, the acquisition time is the time taken to return from 900kHz to 1MHz 5kHz. 5kHz = 5% of the 100kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. 8.9.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 135 Clock Generator Module (CGM) The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is under user control via the choice of crystal frequency fXCLK and the R value programmed in the reference divider. (See 8.4.3 PLL Circuits, 8.4.6 Programming the PLL, and 8.6.5 PLL Reference Divider Select Register.) Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. (See 8.9.3 Choosing a Filter.) Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. Data Sheet 136 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Acquisition/Lock Time Specifications 8.9.3 Choosing a Filter As described in 8.9.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in Figure 8-10 is recommended when using a 32.768kHz reference clock (CGMRCLK). Figure 8-10 (a) is used for applications requiring better stability. Figure 8-10 (b) is used in low-cost applications where stability is not critical. CGMXFC CGMXFC 10 k 0.033 F 0.01 F 0.47 F VSSA VSSA (a) (b) Figure 8-10. PLL Filter MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Data Sheet 137 Clock Generator Module (CGM) Data Sheet 138 Clock Generator Module (CGM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 9. System Integration Module (SIM) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 142 9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . . 143 9.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 144 9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 144 9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 145 9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . 147 9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .148 9.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 148 9.4.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . . 148 9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 149 9.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 149 9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 149 9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.6.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .153 9.6.1.4 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 153 9.6.1.5 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.1.6 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 155 9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 139 System Integration Module (SIM) 9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 156 9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 161 9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 162 9.2 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 9-1. Table 9-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources Table 9-1 shows the internal signal names used in this section. Data Sheet 140 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM, OSC) SIM COUNTER COP CLOCK ICLK (FROM OSC) CGMOUT (FROM CGM) /2 VDD INTERNAL PULLUP DEVICE RESET PIN LOGIC CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS LVI (FROM LVI MODULE) POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU INTERFACE Figure 9-1. SIM Block Diagram Table 9-1. Signal Name Conventions Signal Name ICLK CGMXCLK CGMPCLK CGMOUT IAB IDB PORRST IRST R/W Internal RC oscillator clock Buffered version of OSC1 from the oscillator module The divided PLL output PLL-based or oscillator-based clock output from CGM module (Bus clock = CGMOUT / 2) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal Description MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 141 System Integration Module (SIM) Addr. Register Name Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR: $FE03 Read: SIM Break Flag Control Register Write: (SBFCR) Reset: POR 1 BCFE 0 IF6 R 0 IF14 R 0 0 R 0 PIN 0 R COP 0 R ILOP 0 R ILAD 0 R 0 0 R LVI 0 R 0 0 R Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: IF5 R 0 IF13 R 0 0 R 0 IF4 R 0 IF12 R 0 0 R 0 IF3 R 0 IF11 R 0 0 R 0 IF2 R 0 IF10 R 0 IF18 R 0 R IF1 R 0 IF9 R 0 IF17 R 0 = Reserved 0 R 0 IF8 R 0 IF16 R 0 0 R 0 IF7 R 0 IF15 R 0 = Unimplemented Figure 9-2. SIM I/O Register Summary 9.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come from either the oscillator module or from the on-chip PLL. (See Section 8. Clock Generator Module (CGM).) Data Sheet 142 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) SIM Bus Clock Control and Generation OSC2 OSCILLATOR (OSC) MODULE OSC1 CGMXCLK TO RTC, ADC ICLK STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 SIM COUNTER SYSTEM INTEGRATION MODULE SIMOSCEN IT12 TO REST OF MCU IT23 TO REST OF MCU CGMRCLK CGMOUT PHASE-LOCKED LOOP (PLL) /2 BUS CLOCK GENERATORS SIMDIV2 PTC1 MONITOR MODE USER MODE Figure 9-3. CGM Clock Signals 9.3.1 Bus Timing In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four, CGMXCLK divided by two, or the PLL output (CGMPCLK) divided by four. 9.3.2 Clock Start-up from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 143 System Integration Module (SIM) 9.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 ICLK cycles. (See 9.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 9.4 Reset and System Initialization The MCU has these reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 9.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 9.8 SIM Registers.) Data Sheet 144 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Reset and System Initialization 9.4.1 External Pin Reset The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 ICLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 9-2 for details. Figure 9-4 shows the relative timing. Table 9-2. PIN Bit Set Timing Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3) CGMOUT RST IAB PC VECT H VECT L Figure 9-4. External Reset Timing 9.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 9-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 9-6). NOTE: For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 9-5. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 145 System Integration Module (SIM) IRST RST ICLK RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES IAB VECTOR HIGH Figure 9-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 9-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 9.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: * * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables CGMOUT. Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. MC68HC908LJ24/LK24 -- Rev. 2.1 System Integration Module (SIM) Freescale Semiconductor Data Sheet 146 System Integration Module (SIM) Reset and System Initialization OSC1 PORRST 4096 CYCLES ICLK 32 CYCLES 32 CYCLES CGMOUT RST IRST IAB $FFFE $FFFF Figure 9-7. POR Recovery 9.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 213 - 24 ICLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 147 System Integration Module (SIM) 9.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 9.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. 9.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI trip falling voltage, VTRIPF. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 9.4.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are blank ($FF). (See Section 10. Monitor ROM (MON).) When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. Data Sheet 148 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) SIM Counter 9.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of ICLK. 9.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. 9.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. 9.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 9.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 9.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 149 System Integration Module (SIM) 9.6 Exception Control Normal, sequential program execution can be changed in three different ways: * Interrupts: - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * 9.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 9-8 shows interrupt entry timing, and Figure 9-9 shows interrupt recovery timing. MODULE INTERRUPT I-BIT IAB IDB R/W DUMMY DUMMY SP SP - 1 SP - 2 X SP - 3 A SP - 4 CCR VECT H VECT L START ADDR OPCODE Reset Break interrupts PC - 1[7:0] PC - 1[15:8] V DATA H V DATA L Figure 9-8. Interrupt Entry Timing MODULE INTERRUPT I-BIT IAB IDB R/W SP - 4 CCR SP - 3 A SP - 2 X SP - 1 SP PC PC + 1 OPCODE OPERAND PC - 1[15:8] PC - 1[7:0] Figure 9-9. Interrupt Recovery Timing Data Sheet 150 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Exception Control Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 9-10.) FROM RESET BREAK I BIT SET? INTERRUPT? NO YES YES I-BIT SET? NO IRQ INTERRUPT? NO YES AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? NO RTI INSTRUCTION? NO YES YES UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Figure 9-10. Interrupt Processing MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 151 System Integration Module (SIM) 9.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 9-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. CLI LDA #$FF BACKGROUND ROUTINE INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 9-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908LJ24/LK24 -- Rev. 2.1 System Integration Module (SIM) Freescale Semiconductor Data Sheet 152 System Integration Module (SIM) Exception Control 9.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does. 9.6.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. 9.6.1.4 Interrupt Status Register 1 Address: $FE04 Bit 7 Read: Write: Reset: IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0 Figure 9-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 153 System Integration Module (SIM) Table 9-3. Vector Addresses Priority Lowest INT Flag IF18 IF17 IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector Real Time Clock Vector (High) Real Time Clock Vector (Low) ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) MMIIC Vector (High) MMIIC Vector (Low) SCI Transmit Vector (High) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) TIM2 Overflow Vector (High) TIM2 Overflow Vector (Low) TIM2 Channel 1 Vector (High) TIM2 Channel 1 Vector (Low) TIM2 Channel 0 Vector (High) TIM2 Channel 0 Vector (Low) TIM1 Overflow Vector (High) TIM1 Overflow Vector (Low) TIM1 Channel 1 Vector (High) TIM1 Channel 1 Vector (Low) TIM1 Channel 0 Vector (High) TIM1 Channel 0 Vector (Low) PLL Vector (High) PLL Vector (Low) LVI Vector (High) LVI Vector (Low) IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) Highest Data Sheet 154 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Exception Control 9.6.1.5 Interrupt Status Register 2 Address: $FE05 Bit 7 Read: Write: Reset: IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0 Figure 9-13. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present 9.6.1.6 Interrupt Status Register 3 Address: $FE06 Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 IF18 R 0 2 IF17 R 0 1 IF16 R 0 Bit 0 IF15 R 0 Figure 9-14. Interrupt Status Register 3 (INT3) IF18-IF15 -- Interrupt Flags 18-15 These flags indicate the presence of an interrupt request from the source shown in Table 9-3. 1 = Interrupt request present 0 = No interrupt request present MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 155 System Integration Module (SIM) 9.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 9.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 23. Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. Data Sheet 156 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Low-Power Modes 9.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 9.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 9-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. IAB WAIT ADDR WAIT ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 9-15. Wait Mode Entry Timing Figure 9-16 and Figure 9-17 show the timing for WAIT recovery. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 157 System Integration Module (SIM) IAB $6E0B $6E0C $00FF $00FE $00FD $00FC IDB $A6 $A6 $A6 $01 $0B $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 9-16. Wait Recovery from Interrupt or Break 32 CYCLES IAB $6E0B 32 CYCLES RST VCT H RST VCT L IDB $A6 $A6 $A6 RST ICLK Figure 9-17. Wait Recovery from Internal Reset 9.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. Data Sheet 158 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) SIM Registers A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 9-18 shows stop mode entry timing. NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. CPUSTOP IAB STOP ADDR STOP ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 9-18. Stop Mode Entry Timing STOP RECOVERY PERIOD ICLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP - 1 SP - 2 SP - 3 Figure 9-19. Stop Mode Recovery from Interrupt or Break 9.8 SIM Registers The SIM has three memory-mapped registers: * * * MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) SIM Break Status Register (SBSR) -- $FE00 SIM Reset Status Register (SRSR) -- $FE01 SIM Break Flag Control Register (SBFCR) -- $FE03 Data Sheet 159 System Integration Module (SIM) 9.8.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: $FE00 Bit 7 Read: Write: Reset: Note: Writing a logic 0 clears SBSW. 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R R R = Reserved Figure 9-20. SIM Break Status Register (SBSR) SBSW -- Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it. The following code is an example. This code works if the H register has been pushed onto the stack in the break service routine software. This code should be executed at the end of the break service routine software. HIBYTE LOBYTE EQU EQU If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register. Data Sheet 160 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) SIM Registers 9.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: $FE01 Bit 7 Read: Write: Reset: 1 0 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 0 1 LVI Bit 0 0 = Unimplemented Figure 9-21. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) Data Sheet 161 System Integration Module (SIM) 9.8.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R Figure 9-22. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 162 System Integration Module (SIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 10.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.4.3 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 10.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10.6 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10.6.1 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10.6.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 10.6.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 10.6.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 10.6.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.6.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.6.7 EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10.6.8 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 163 Monitor ROM (MON) 10.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. In addition, to simplify user coding, routines are also stored in the monitor ROM area for FLASH memory program /erase and EEPROM emulation. 10.3 Features Features of the monitor ROM include: * * * * * * * * * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in RAM or FLASH FLASH memory security feature1 FLASH memory programming interface Enhanced PLL (phase-locked loop) option to allow use of external 32.768-kHz crystal to generate internal frequency of 2.4576 MHz 959 bytes monitor ROM code size ($FC00-$FDFF and $FE10-$FFCE) Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage, VTST, is applied to IRQ Resident routines for in-circuit programming and EEPROM emulation 1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 164 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Functional Description 10.4 Functional Description The monitor ROM receives and executes commands from a host computer. Figure 10-1 shows an example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code allows enabling the PLL to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal. This entry method, which is enabled when IRQ is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode by stepping up the external frequency (assumed to be 32.768 kHz) by a fixed amount to generate the desired internal frequency (2.4576 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is non-zero because entry into monitor mode in this case requires VTST on IRQ. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 165 Monitor ROM (MON) RST 0.1 F VDD HC908LJ24 VDD 0.1 F VDDA VLCD VREFH VSS VDD 4.9152MHz/9.8304MHz (50% DUTY) OSC1 10k 0.01 F VREFL CGMXFC MUST BE USED IF SW2 IS AT POSITION C. CONNECT TO OSC1, WITH OSC2 UNCONNECTED. EXT OSC 6-30 pF MAX232 1 1 F + 3 4 1 F + C1+ C1- C2+ VCC GND V+ V- 16 + 15 + 2 6 + 7 8 10 9 2 74HC125 3 1 10 k A (SEE NOTE 2) NOTES: 1. Monitor mode entry method: SW2: Position C -- High voltage entry (VTST); must use external OSC Bus clock depends on SW1 (note 2). SW2: Position D -- Reset vector must be blank ($FFFE:$FFFF = $FF) Bus clock = 2.4576MHz. 2. Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A -- Bus clock = OSC1 / 4 SW1: Position B -- Bus clock = OSC1 / 2 5. See Table 24-4 for VTST voltage level requirements. B 1 F 74HC125 5 6 4 VDD 1 F 1 F VTST VDD 10 k 1k 8.5 V XTAL CIRCUIT C D VDD 32.768kHz 330k 6-30 pF 10M 0.033 F OSC1 OSC2 SW2 (SEE NOTE 1) IRQ 5 C2- DB9 2 3 5 PTA0 VDD 10 k SW1 PTA1 PTC1 PTA2 10 k 10 k Figure 10-1. Monitor Mode Circuit Data Sheet 166 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Functional Description 10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF do not contain $FF (programmed state): - The external clock is 4.9152 MHz with PTC1 low or 9.8304 MHz with PTC1 high - IRQ = VTST (PLL off) 2. If $FFFE and $FFFF both contain $FF (erased state): - The external clock is 9.8304 MHz - IRQ = VDD (this can be implemented through the internal IRQ pullup; PLL off) 3. If $FFFE and $FFFF both contain $FF (erased state): - The external clock is 32.768 kHz (crystal) - IRQ = VSS (this setting initiates the PLL to boost the external 32.768 kHz to an internal bus frequency of 2.4576 MHz) If VTST is applied to IRQ and PTC1 is low upon monitor mode entry (above condition set 1), the bus frequency is a divide-by-two of the input clock. If PTC1 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC1 pin low when entering monitor mode causes a bypass of a divideby-two stage at the oscillator only if VTST is applied to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage is either VDD or VSS), then all port A pin requirements and conditions, including the PTC1 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 167 168 Monitor ROM (MON) Freescale Semiconductor Data Sheet IRQ X RST GND Address $FFFE/ $FFFF X VTST(3) VDD or VTST X VTST(3) VDD or VTST X VDD GND VDD VDD Blank "$FFFF" Blank "$FFFF" VDD or GND VDD or GND VTST Blank "$FFFF" Monitor ROM (MON) Table 10-1. Monitor Mode Signal Requirements and Options PTA2 X PTA1 X PTA0(1) X PTC1 X External Clock(2) X Bus Frequency 0 PLL X COP Disabled Baud Rate 0 Comment No operation until reset goes high PTA1 and PTA2 voltages only required if IRQ = VTST; PTC1 determines frequency divider PTA1 and PTA2 voltages only required if IRQ = VTST; PTC1 determines frequency divider External frequency always divided by 4 PLL enabled (BCS set) in monitor code Enters user mode -- will encounter an illegal address reset Enters user mode 0 1 1 0 4.9152 MHz 2.4576 MHz OFF Disabled 9600 0 1 1 1 9.8304 MHz 2.4576 MHz OFF Disabled 9600 X X 1 X 9.8304 MHz 32.768 kHz 2.4576 MHz 2.4576 MHz OFF Disabled 9600 X X 1 X ON Disabled 9600 X X X X X -- OFF Enabled -- MC68HC908LJ24/LK24 -- Rev. 2.1 VDD or VTST Not Blank X X X X X -- OFF Enabled -- Notes: 1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication 2. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator 3. Monitor mode entry by IRQ = VTST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is bypassed. Monitor ROM (MON) Functional Description NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. The COP module is disabled in monitor mode based on these conditions: * If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the COP is always disabled regardless of the state of IRQ or RST. If monitor mode was entered with VTST on IRQ (condition set 1), then the COP is disabled as long as VTST is applied to either IRQ or RST. * The second condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. Figure 10-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just 1 x VDD voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. Enter monitor mode with pin configuration shown in Figure 10-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 10.5 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 169 Monitor ROM (MON) POR RESET IS VECTOR BLANK? YES MONITOR MODE NO NORMAL USER MODE EXECUTE MONITOR CODE POR TRIGGERED? YES NO Figure 10-2. Low-Voltage Monitor Mode Entry Flowchart In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE: Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. Table 10-2 summarizes the differences between user mode and monitor mode vectors. Table 10-2. Mode Differences (Vectors) Functions Modes Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD User Monitor Data Sheet 170 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Functional Description 10.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. NEXT START STOP BIT BIT START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Figure 10-3. Monitor Data Format 10.4.3 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 10-4. Break Transaction 10.4.4 Baud Rate The communication baud rate is controlled by the crystal frequency and the state of the PTC1 pin (when IRQ is set to VTST) upon entry into monitor mode. When PTC1 is high, the divide by ratio is 1024. If the PTC1 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512. If monitor mode was entered with VDD on IRQ, then the divide by ratio is set at 1024, regardless of PTC1. If monitor mode was entered with VSS on IRQ, then the internal PLL steps up the external frequency, presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require that the reset vector is blank. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 171 Monitor ROM (MON) Table 10-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other standard baud rates can be accomplished using proportionally higher or lower frequency generators. If using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. Table 10-3. Monitor Baud Rate Selection External Frequency 4.9152 MHz 9.8304 MHz 9.8304 MHz 32.768 kHz IRQ VTST VTST VDD VSS PTC1 0 1 X X Internal Frequency 2.4576 MHz 2.4576 MHz 2.4576 MHz 2.4576 MHz Baud Rate (BPS) 9600 9600 9600 9600 10.4.5 Commands The monitor ROM firmware uses these commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE: Wait one bit time after each echo before sending the next byte. Data Sheet 172 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Functional Description FROM HOST READ READ ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA 4 ECHO 1 4 1 4 1 3, 2 4 RETURN Notes: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 10-5. Read Transaction FROM HOST WRITE 3 ECHO 1 WRITE 3 ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA 1 3 1 3 1 2, 3 Notes: 1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 10-6. Write Transaction A brief description of each monitor mode command is given in Table 10-4 through Table 10-9. Table 10-4. READ (Read Memory) Command Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence SENT TO MONITOR READ READ ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA ECHO RETURN MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 173 Monitor ROM (MON) Table 10-5. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 10-6. IREAD (Indexed Read) Command Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA DATA ECHO RETURN Data Sheet 174 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Functional Description Table 10-7. IWRITE (Indexed Write) Command Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 10-8. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP READSP SP HIGH SP LOW ECHO RETURN MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 175 Monitor ROM (MON) Table 10-9. RUN (Run User Program) Command Description Operand Data Returned Opcode Executes PULH and RTI instructions None None $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6. SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER SP + 1 SP + 2 SP + 3 SP + 4 HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7 Figure 10-7. Stack Pointer at Monitor Mode Entry Data Sheet 176 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Security 10.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 10-8.) VDD 4096 + 32 ICLK CYCLES RST COMMAND 2 BYTE 8 ECHO 4 1 COMMAND ECHO BREAK 256 BUS CYCLES (MINIMUM) BYTE 1 BYTE 2 BYTE 8 1 BYTE 2 ECHO 1 FROM HOST PTA0 1 BYTE 1 ECHO FROM MCU 4 NOTES: 1 = Echo delay, 2 bit times. 2 = Data return delay, 2 bit times. 4 = Wait 1 bit time before sending next byte. Figure 10-8. Monitor Mode Entry Timing MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 177 Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bits. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Data Sheet 178 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines 10.6 ROM-Resident Routines Eight routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory manipulation. Six of the eight routines are intended to simplify FLASH program, erase, and load operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM. Table 10-10 shows a summary of the ROM-resident routines. Table 10-10. Summary of ROM-Resident Routines Routine Name PRGRNGE ERARNGE LDRNGE MON_PRGRNGE MON_ERARNGE MON_LDRNGE EE_WRITE EE_READ Routine Description Program a range of locations Erase a page or the entire array Loads data from a range of locations Program a range of locations in monitor mode Erase a page or the entire array in monitor mode Loads data from a range of locations in monitor mode Emulated EEPROM write. Data size ranges from 2 to 15 bytes at a time. Emulated EEPROM read. Data size ranges from 2 to 15 bytes at a time. Call Address $FC06 $FCBE $FF30 $FF28 $FF2C $FF24 $FC00 $FC03 Stack Used (bytes) 14 9 9 16 11 11 17 15 The routines are designed to be called as stand-alone subroutines in the user program or monitor mode. The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM. The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used, any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in Figure 10-9. During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 179 Monitor ROM (MON) R $XXXX ADDRESS AS POINTER FILE_PTR A M BUS SPEED (BUS_SPD) DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA 1 DATA BLOCK DATA ARRAY DATA N Figure 10-9. Data Block Format for ROM-Resident Routines The control and data bytes are described below. * Bus speed -- This one byte indicates the operating bus speed of the MCU. The value of this byte should be equal to 4 times the bus speed. E.g., for a 4MHz bus, the value is 16 ($10). This control byte is useful where the MCU clock source is switched between the PLL clock and the crystal clock. Data size -- This one byte indicates the number of bytes in the data array that are to be manipulated. The maximum data array size is 255. Routines EE_WRITE and EE_READ are restricted to manipulate a data array between 2 to 15 bytes. Whereas routines ERARNGE and MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning. Start address -- These two bytes, high byte followed by low byte, indicate the start address of the FLASH memory to be manipulated. Data array -- This data array contains data that are to be manipulated. Data in this array are programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE, EE_WRITE. For the read routines: LDRNGE, MON_LDRNGE, and EE_READ, data is read from FLASH and stored in this array. MC68HC908LJ24/LK24 -- Rev. 2.1 Monitor ROM (MON) Freescale Semiconductor * * * Data Sheet 180 Monitor ROM (MON) ROM-Resident Routines 10.6.1 PRGRNGE PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 10-11. PRGRNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format PRGRNGE Program a range of locations $FC06 14 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be programmed in one routine call is 255 bytes (max. DATASIZE is 255). ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment during programming. A check to see that all bytes in the specified range are erased is not performed by this routine prior programming. Nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. User must assure that the range specified is first erased. The coding example below is to program 64 bytes of data starting at FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 181 Monitor ROM (MON) ORG : FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY PRGRNGE FLASH_START RAM DS.B DS.B DS.W DS.B EQU EQU 1 1 1 64 $FC06 $EF00 ; ; ; ; Indicates 4x bus frequency Data size to be programmed FLASH start address Reserved data array ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE Data Sheet 182 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines 10.6.2 ERARNGE ERARNGE is used to erase a range of locations in FLASH. Table 10-12. ERARNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format ERARNGE Erase a page or the entire array $FCBE 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (128 consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass erase. The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not used. The coding example below is to perform a page erase, from $EF00-$EF7F. The Initialization subroutine is the same as the coding example for PRGRNGE (see 10.6.1 PRGRNGE). ERARNGE MAIN: BSR : : LDHX JSR : EQU $FCBE INITIALISATION #FILE_PTR ERARNGE MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 183 Monitor ROM (MON) 10.6.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 10-13. LDRNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format LDRNGE Loads data from a range of locations $FF30 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be retrieved in one routine call is 255 bytes. The data retrieved from FLASH is loaded into the data array in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from FLASH that was previously programmed. The coding example below is to retrieve 64 bytes of data starting from $EF00 in FLASH. The Initialization subroutine is the same as the coding example for PRGRNGE (see 10.6.1 PRGRNGE). LDRNGE MAIN: BSR : : LDHX JSR : EQU $FF30 INITIALIZATION #FILE_PTR LDRNGE Data Sheet 184 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines 10.6.4 MON_PRGRNGE In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 10-14. MON_PRGRNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format MON_PRGRNGE Program a range of locations, in monitor mode $FC28 16 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Data 1 : Data N The MON_PRGRNGE routine is designed to be used in monitor mode. It performs the same function as the PRGRNGE routine (see 10.6.1 PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 185 Monitor ROM (MON) 10.6.5 MON_ERARNGE In monitor mode, ERARNGE is used to erase a range of locations in FLASH. Table 10-15. MON_ERARNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format MON_ERARNGE Erase a page or the entire array, in monitor mode $FF2C 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as the ERARNGE routine (see 10.6.2 ERARNGE), except that MON_ERARNGE returns to the main program via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code. Data Sheet 186 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines 10.6.6 MON_LDRNGE In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 10-16. ICP_LDRNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format MON_LDRNGE Loads data from a range of locations, in monitor mode $FF24 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Data 1 : Data N The MON_LDRNGE routine is designed to be used in monitor mode. It performs the same function as the LDRNGE routine (see 10.6.3 LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 187 Monitor ROM (MON) 10.6.7 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Table 10-17. EE_WRITE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format EE_WRITE Emulated EEPROM write. Data size ranges from 2 to 15 bytes at a time. $FC00 17 bytes Bus speed (BUS_SPD) Data size (DATASIZE)(1) Starting address (ADDRH)(2) Starting address (ADDRL)(1) Data 1 : Data N Notes: 1. The minimum data size is 2 bytes. The maximum data size is 15 bytes. 2. The start address must be a page boundary start address, e.g. $xx00 or $xx80. The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be programmed in one routine call is 2 bytes, the maximum is 15 bytes. ADDRH:ADDRL must always be the start of boundary address (the page start address: $XX00 or $0080) and DATASIZE must be the same size when accessing the same page. In some applications, the user may want to repeatedly store and read a set of data from an area of non-volatile memory. This is easily possible when using an EEPROM array. As the write and erase operations can be executed on a byte basis. For FLASH memory, the minimum erase size is the page -- 128 bytes per page for MC68HC908LJ24. If the data array size is less than the page size, writing and erasing to the same page cannot fully utilize the page. Unused locations in the page will be wasted. The EE_WRITE routine is designed to emulate the properties similar to the EEPROM. Allowing a more efficient use of the FLASH page for data storage. Data Sheet 188 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines When the user dedicates a page of FLASH for data storage, and the size of the data array defined, each call of the EE_WRTIE routine will automatically transfer the data in the data array (in RAM) to the next blank block of locations in the FLASH page. Once a page is filled up, the EE_WRITE routine automatically erases the page, and starts reuse the page again. In the 128-byte page, an 8-byte control block is used by the routine to monitor the utilization of the page. In effect, only 120 bytes are used for data storage. (see Figure 10-10). The page control operations are transparent to the user. FLASH PAGE BOUNDARY CONTROL: 8 BYTES DATA ARRAY DATA ARRAY DATA ARRAY ONE PAGE = 128 BYTES $XX00 OR $XX80 PAGE BOUNDARY Figure 10-10. EE_WRITE FLASH Memory Usage When using this routine to store a 2-byte data array, the FLASH page can be programmed 60 times before the an erase is required. In effect, the write/erase endurance is increased by 60 times. When a 15-byte data array is used, the write/erase endurance is increased by 8 times. Due to the FLASH page size limitation, the data array is limited from 2 bytes to 15 bytes. The coding example below uses the $EF00-$EE7F page for data storage. The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) Data Sheet 189 Monitor ROM (MON) ORG : FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY EE_WRITE FLASH_START RAM DS.B DS.B DS.W DS.B EQU EQU 1 1 1 15 $FC00 $EF00 ; ; ; ; Indicates 4x bus frequency Data size to be programmed FLASH starting address Reserved data array ORG FLASH INITIALISATION: MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS MAIN: BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE NOTE: The EE_WRITE routine is unable to check for incorrect data blocks, such as the FLASH page boundary address and data size. It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 2 to 15. If the FLASH page is already programmed with a data array with a different size, the EE_WRITE call will be ignored. Data Sheet 190 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) ROM-Resident Routines 10.6.8 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Table 10-18. EE_READ Routine Routine Name Routine Description Calling Address Stack Used Data Block Format EE_READ Emulated EEPROM read. Data size ranges from 2 to 15 bytes at a time. $FC03 15 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH)(1) Starting address (ADDRL)(1) Data 1 : Data N Notes: 1. The start address must be a page boundary start address, e.g. $xx00 or $xx80. The EE_READ routine reads data stored by the EE_WRITE routine. An EE_READ call will retrieve the last data written to a FLASH page and loaded into the data array in RAM. Same as EE_WRITE, the data size indicated by DATASIZE is 2 to 15, and the start address ADDRH:ADDRL must the FLASH page boundary address. The coding example below uses the data stored by the EE_WRITE coding example (see 10.6.7 EE_WRITE). It loads the 15-byte data set stored in the $EF00-$EE7F page to the data array in RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see 10.6.7 EE_WRITE). EE_READ MAIN: BSR : : LDHX JSR : MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Monitor ROM (MON) INITIALIZATION EQU $FC03 #FILE_PTR EE_READ Data Sheet 191 Monitor ROM (MON) NOTE: The EE_READ routine is unable to check for incorrect data blocks, such as the FLASH page boundary address and data size. It is the responsibility of the user to ensure the starting address indicated in the data block is at the FLASH page boundary and the data size is 2 to 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Data Sheet 192 Monitor ROM (MON) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 11.3 11.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 200 11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .201 11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 201 11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 202 11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 203 11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 206 11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.9.1 TIM Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 11.9.2 TIM Channel I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 208 11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 211 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 212 11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 193 Timer Interface Module (TIM) 11.2 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 11.3 Features Features of the TIM include: * Two input capture/output compare channels: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * * Buffered and unbuffered pulse-width-modulation (PWM) signal generation Programmable TIM clock input - 7-frequency internal bus clock prescaler selection - External TIM clock input (bus frequency /2 maximum) * * * Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits Data Sheet 194 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Pin Name Conventions 11.4 Pin Name Conventions The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0). T[1,2]CH1 (timer channel 1), and T[1,2]CLK (external timer clock), where "1" is used to indicate TIM1 and "2" is used to indicate TIM2. The full names of the TIM I/O pins are listed in Table 11-1. The generic pin names appear in the text that follows. Table 11-1. Pin Name Conventions TIM Generic Pin Names: Full TIM Pin Names: TIM1 TIM2 T[1,2]CH0 PTB2/T1CH0 PTB4/T2CH0 T[1,2]CH1 PTB3/T1CH1 PTB5/T2CH1 T[1,2]CLK PTD4/KBI4/T1CLK PTD5/KBI5/T2CLK NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. The T1CLK and T2CLK pins are also shared with KBI4 and KBI5 respectively. To avoid erratic behavior, these two pins should never be configured for use as TCLK and KBI inputs simultaneously. 11.5 Functional Description Figure 11-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 195 Timer Interface Module (TIM) T[1,2]CLK INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC T[1,2]CH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC T[1,2]CH0 PRESCALER SELECT PRESCALER PS2 PS1 PS0 TOF TOIE INTERRUPT LOGIC Figure 11-1. TIM Block Diagram Figure 11-2 summarizes the timer registers. NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC. Data Sheet 196 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Functional Description Addr. Register Name Read: Timer 1 Status and Control Register Write: (T1SC) Reset: Read: Timer 1 Counter Register High Write: (T1CNTH) Reset: Read: Timer 1 Counter Register Low Write: (T1CNTL) Reset: Read: Timer 1 Counter Modulo Register High Write: (T1MODH) Reset: Read: Timer 1 Counter Modulo Register Low Write: (T1MODL) Reset: Bit 7 TOF 0 0 Bit 15 6 TOIE 0 14 5 TSTOP 1 13 4 0 TRST 0 12 3 0 2 PS2 0 10 1 PS1 0 9 Bit 0 PS0 0 Bit 8 $0020 0 11 $0021 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 $0022 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 0 14 1 6 1 CH0IE 0 14 0 13 1 5 1 MS0B 0 13 0 12 1 4 1 MS0A 0 12 0 11 1 3 1 ELS0B 0 11 0 10 1 2 1 ELS0A 0 10 0 9 1 1 1 TOV0 0 9 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 $0023 $0024 Read: Timer 1 Channel 0 Status $0025 and Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 Register Low Write: (T1CH0L) Reset: $0026 Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0 $0027 Indeterminate after reset CH1F 0 0 CH1IE 0 0 MS1A 0 ELS1B 0 ELS1A 0 TOV1 0 CH1MAX 0 Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: 0 = Unimplemented Figure 11-2. TIM I/O Register Summary (Sheet 1 of 3) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 197 Timer Interface Module (TIM) Addr. Register Name Read: Timer 1 Channel 1 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 Register Low Write: (T1CH1L) Reset: Read: Timer 2 Status and Control Register Write: (T2SC) Reset: Read: Timer 2 Counter Register High Write: (T2CNTH) Reset: Read: Timer 2 Counter Register Low Write: (T2CNTL) Reset: Read: Timer 2 Counter Modulo Register High Write: (T2MODH) Reset: Read: Timer 2 Counter Modulo Register Low Write: (T2MODL) Reset: Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 $0029 Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0 $002A Indeterminate after reset TOF 0 0 Bit 15 TOIE 0 14 TSTOP 1 13 0 TRST 0 12 0 11 0 PS2 0 10 PS1 0 9 PS0 0 Bit 8 $002B $002C 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 $002D 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 0 14 1 6 1 CH0IE 0 14 0 13 1 5 1 MS0B 0 13 0 12 1 4 1 MS0A 0 12 0 11 1 3 1 ELS0B 0 11 0 10 1 2 1 ELS0A 0 10 0 9 1 1 1 TOV0 0 9 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 $002E $002F Read: Timer 2 Channel 0 Status $0030 and Control Register Write: (T2SC0) Reset: Read: Timer 2 Channel 0 Register High Write: (T2CH0H) Reset: $0031 Indeterminate after reset = Unimplemented Figure 11-2. TIM I/O Register Summary (Sheet 2 of 3) Data Sheet 198 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Functional Description Addr. Register Name Read: Timer 2 Channel 0 Register Low Write: (T2CH0L) Reset: Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 $0032 Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8 Read: Timer 2 Channel 1 Status $0033 and Control Register Write: (T2SC1) Reset: Read: Timer 2 Channel 1 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 Register Low Write: (T2CH1L) Reset: 0 13 $0034 Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0 $0035 Indeterminate after reset = Unimplemented Figure 11-2. TIM I/O Register Summary (Sheet 3 of 3) 11.5.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source. 11.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 199 Timer Interface Module (TIM) 11.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 11.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. * Data Sheet 200 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Functional Description 11.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 11-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 201 Timer Interface Module (TIM) The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 11.10.1 TIM Status and Control Register. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 11-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 11.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 11.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Data Sheet 202 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Functional Description Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. * NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 11.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 203 Timer Interface Module (TIM) NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 11.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 11-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 11-3.) NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Data Sheet 204 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Interrupts Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM channel 0 status and control register (TSC0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 11.10.4 TIM Channel Status and Control Registers.) 11.6 Interrupts The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register. * 11.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 205 Timer Interface Module (TIM) 11.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 11.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 11.8 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 9.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Data Sheet 206 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) I/O Signals 11.9 I/O Signals Port B shares four of its pins with the TIM channel I/O pins: T1CH0, T1CH1, T2CH0, and T2CH1. Port D shares two of its pins with the TIM clock input pins: T1CLK and T2CLK 11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK) T[1,2]CLK is an external clock input that can be the clock source for the TIM[1,2] counter instead of the prescaled internal bus clock. Select the T[1,2]CLK input by writing logic 1's to the three prescaler select bits, PS[2:0]. (See 11.10.1 TIM Status and Control Register.) The minimum T[1,2]CLK pulse width, T[1,2]CLKLMIN or T[1,2]CLKHMIN, is: 1 ------------------------------------ + t SU bus frequency The maximum T[1,2]CLK frequency is: bus frequency / 2 T1CLK and T2CLK are available as standard I/Os or KBI pins when not used as the TIM clock inputs. 11.9.2 TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1, PTB4/T2CH0, PTB5/T2CH1) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 207 Timer Interface Module (TIM) 11.10 I/O Registers NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: * * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0, TSC1) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) 11.10.1 TIM Status and Control Register The TIM status and control register (TSC): * * * * * Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0 = Unimplemented Figure 11-4. TIM Status and Control Register (TSC) Data Sheet 208 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) I/O Registers TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. Data Sheet Timer Interface Module (TIM) 209 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 11-2 shows. Reset clears the PS[2:0] bits. Table 11-2. Prescaler Selection PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 TCLK 11.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Address: T1CNTH, $0021 and T2CNTH, $002C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 = Unimplemented Figure 11-5. TIM Counter Registers High (TCNTH) Data Sheet 210 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) I/O Registers Address: T1CNTL, $0022 and T2CNTL, $002D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 = Unimplemented Figure 11-6. TIM Counter Registers Low (TCNTL) 11.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Address: T1MODH, $0023 and T2MODH, $002E Bit 7 Read: Write: Reset: Bit 15 1 6 14 1 5 13 1 4 12 1 3 11 1 2 10 1 1 9 1 Bit 0 Bit 8 1 Figure 11-7. TIM Counter Modulo Register High (TMODH) Address: T1MODL, $0024 and T2MODL, $002F Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1 Figure 11-8. TIM Counter Modulo Register Low (TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 211 Timer Interface Module (TIM) 11.10.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation Address: T1SC0, $0025 and T2SC0, $0030 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0 Figure 11-9. TIM Channel 0 Status and Control Register (TSC0) Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 Read: Write: Reset: CH1F 0 0 6 CH1IE 0 5 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0 0 = Unimplemented Figure 11-10. TIM Channel 1 Status and Control Register (TSC1) Data Sheet 212 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) I/O Registers CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 11-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 213 Timer Interface Module (TIM) When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 11-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 11-3. Mode, Edge, and Level Selection MSxB:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X ELSxB:ELSxA 00 Output preset 00 01 10 11 01 10 11 01 10 11 Output compare or PWM Buffered output compare or buffered PWM Input capture Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Mode Configuration Pin under port control; initial output level high Data Sheet 214 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) I/O Registers NOTE: Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. User software should also clear CHxF before setting CHxIE to avoid any false interrupts. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow NOTE: When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 11-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW PERIOD TCHx OVERFLOW OVERFLOW OVERFLOW OVERFLOW OUTPUT COMPARE CHxMAX OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 11-11. CHxMAX Latency 11.10.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Timer Interface Module (TIM) Data Sheet 215 Timer Interface Module (TIM) In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 Indeterminate after reset Figure 11-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset Figure 11-13. TIM Channel 0 Register Low (TCH0L) Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 Indeterminate after reset Figure 11-14. TIM Channel 1 Register High (TCH1H) Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Indeterminate after reset Figure 11-15. TIM Channel 1 Register Low (TCH1L) Data Sheet 216 Timer Interface Module (TIM) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 12. Real Time Clock (RTC) 12.1 Contents 12.2 12.3 12.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 12.5.1 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 12.5.2 Calendar Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 12.5.3 Alarm Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.4 Chronograph Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.5 Timebase Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.7 RTC Clock Calibration and Compensation . . . . . . . . . . . . . . . 225 12.7.1 Calibration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.8 RTC Register and Bit Write Protection . . . . . . . . . . . . . . . . . . 227 12.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 12.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 12.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 12.10 RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.10.1 RTC Calibration Control Register (RTCCOMR) . . . . . . . . . 231 12.10.2 RTC Calibration Data Register (RTCCDAT) . . . . . . . . . . . 233 12.10.3 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . . 234 12.10.4 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . . 235 12.10.5 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . . 237 12.10.6 Alarm Minute and Hour Registers (ALMR and ALHR) . . . . 240 12.10.7 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.10.8 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.10.9 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 217 Real Time Clock (RTC) 12.10.10 12.10.11 12.10.12 12.10.13 12.10.14 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Year Register (YRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Day-Of-Week Register (DOWR) . . . . . . . . . . . . . . . . . . . . 244 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . 244 12.2 Introduction This section describes the real time clock (RTC) module. The RTC provides real time clock and calendar functions with automatic leap year adjustments. Other functions include alarm interrupt, periodic interrupts, and a chronograph timer. NOTE: This module is designed for a 32.768-kHz oscillator. 12.3 Features Features of the RTC module include: * * 32.768kHz clock input with frequency compensation Counter registers for: - Second - Minute - Hour - Day - Day-of-week - Month - Year * * * * Day counter with automatic month and leap year adjustment 1/100 seconds chronograph counter Seven periodic interrupts Alarm interrupt Data Sheet 218 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) I/O Pins 12.4 I/O Pins Two RTC clock calibration pins are shared with standard port I/O pins. Table 12-1. Pin Name Conventions RTC Generic Pin Name CALIN CALOUT Full MCU Pin Name PTD0/SS/CALIN PTD3/SPSCK/CALOUT (1) Pin Selected for RTC Function by Bits in RTCCOMR ($0040) AUTOCAL OUTF[1:0} Notes: 1. Do not enable the SPI function if the pin is used for RTC calibration. Addr. $0040 Register Name Read: RTC Calibration Control Register Write: (RTCCOMR) Reset: Read: RTC Calibration Data Register Write: (RTCCDAT) Reset: Read: RTC Control Register 1 Write: (RTCCR1) Reset: Bit 7 0 R 0 EOVL U ALMIE 0 6 0 R 0 0 0 CHRIE 0 0 CHRCLR 0 CHRF 0 0 0 5 CAL 0 E5 U DAYIE 0 CHRE 0 DAYF 0 AM5 U 4 AUTOCAL 0 E4 U HRIE 0 RTCE 0 HRF 0 AM4 U 3 OUTF1 0 E3 U MINIE 0 TBH 0 MINF 0 AM3 U 2 OUTF0 0 E2 U SECIE 0 0 0 SECF 0 AM2 U R 1 0 0 E1 U TB1IE 0 0 0 TB1F 0 AM1 U = Reserved Bit 0 0 0 E0 U TB2IE 0 0 0 TB2F 0 AM0 U RTCWE1 RTCWE0 $0041 $0042 $0043 Read: COMEN RTC Control Register 2 Write: (RTCCR2) Reset: U Read: RTC Status Register Write: (RTCSR) Reset: Read: Alarm Minute Register Write: (ALMR) Reset: ALMF 0 0 0 $0044 $0045 Reset by POR only. U = Unaffected = Unimplemented Figure 12-1. RTC I/O Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 219 Real Time Clock (RTC) $0046 Read: Alarm Hour Register Write: (ALHR) Reset: Read: Second Register Write: (SECR) Reset: Read: Minute Register Write: (MINR) Reset: Read: Hour Register Write: (HRR) Reset: Read: Day Register Write: (DAYR) Reset: Read: Month Register Write: (MTHR) Reset: Read: Year Register Write: (YRR) Reset: Read: Day-Of-Week Register Write: (DOWR) Reset: Read: Chronograph Data Register Write: (CHRR) Reset: 0 0 0 0 0 0 0 0 0 0 0 0 YR7 U 0 0 0 0 U = Unaffected 0 0 0 0 0 0 0 0 0 0 0 0 YR6 U 0 0 CHR6 0 0 0 SEC5 U MIN5 U 0 0 0 0 0 0 YR5 U 0 0 CHR5 0 AH4 U SEC4 U MIN4 U HR4 U DAY4 U 0 0 YR4 U 0 0 CHR4 0 AH3 U SEC3 U MIN3 U HR3 U DAY3 U MTH3 U YR3 U 0 0 CHR3 0 AH2 U SEC2 U MIN2 U HR2 U DAY2 U MTH2 U YR2 U DOW2 U CHR2 0 R AH1 U SEC1 U MIN1 U HR1 U DAY1 U MTH1 U YR1 U DOW1 U CHR1 0 = Reserved AH0 U SEC0 U MIN0 U HR0 U DAY0 U MTH0 U YR0 U DOW0 U CHR0 0 $0047 $0048 $0049 $004A $004B $004C $004D $004E = Unimplemented Figure 12-1. RTC I/O Register Summary Data Sheet 220 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Functional Description 12.5 Functional Description The RTC module provides clock indications in seconds, minutes, and hours; calendar indications in day-of-week, day-of-month, month, and year; with automatic adjustment for month and leap year. Reading the clock and calendar registers return the current time and date. Writing to these registers set the time and date, and the counters will continue to count from the new settings. The alarm interrupt is set for the hour and minute. When the hour and minute counters matches the time set in the alarm hour and minute registers, the alarm flag is set. The alarm can be configured to generate a CPU interrupt request. A 1/100 seconds chronograph counter is provided for timing applications. This counter can be independently enabled or disabled, and cleared at any time. RTC module interrupts include the alarm interrupt and seven periodic interrupts from the clock and chronograph counters. A frequency compensation mechanism is built into this RTC module to allow adjustments made to the RTC clock when a less accurate 32.768kHz crystal is used. The 1-Hz clock that drives the clock and calendar could make use of the built-in compensation mechanism for crystal frequency error compensation so that the 1-Hz clock could be made more accurate than the frequency accuracy of the crystal that drive the module. The compensation value can be provided by application software or acquire automatically during calibration operation of the module. Figure 12-2 shows the structure of the RTC module. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 221 Real Time Clock (RTC) CALOUT 1Hz REFERENCE CALIN CLOCK CALIBRATION AND COMPENSATION CIRCUIT 1Hz TO CLOCK COUNTERS /2 /2 /2 2Hz 4Hz 8Hz 16Hz 128 Hz TBH SL TBH = 0 => X,Y = A TBH = 1 => X,Y = B CGMXCLK (32.768kHz) / 256 /2 /2 /2 XA YA XB YB X TB1F TB1IE Y TB2F TB2IE CHRF CHRIE x 25 16 + 32 32 CHRONOGRAPH COUNTER FROM CLOCK COMPENSATION CIRCUIT 1Hz SECF SECIE SECOND COUNTER REGISTER INTERRUPT LOGIC MINF MINIE 1/100 SECONDS CHRONOGRAPH DATA REGISTER CHRE CHRCLR ALARM MINUTE REGISTER COMPARATOR MINUTE COUNTER REGISTER INTERNAL BUS HRF ALARM HOUR REGISTER COMPARATOR HOUR COUNTER REGISTER DAYF DAY-OF-WEEK COUNTER REGISTER DAY COUNTER REGISTER DAYIE HRIE ALMF ALMIE MONTH COUNTER REGISTER YEAR COUNTER REGISTER Figure 12-2. RTC Block Diagram Data Sheet 222 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Functional Description 12.5.1 Time Functions Real time clock functions are provided by the second, minute, and hour counter registers. All three clock counters are able to generate interrupts on every counter increment, providing periodic interrupts for the second (SECF), minute (MINF), and hour (HRF). A CPU interrupt request is generated if the corresponding enable bit (SECIE, MINIE, and HRIE) is also set. 12.5.2 Calendar Functions Calendar functions are provided by the day, day-of-week, month, and year counter registers. The roll over of the day counter is automatically adjusted for the month and leap years. The setting for the year counter ranges from 1901 to 2099. The day flag (DAYF) is set on every increment of the day counter. A CPU interrupt request is generated if the day interrupt enable bit (DAYIE) is also set. 12.5.3 Alarm Functions An alarm function is provided for the minute and hour counters. When minute counter matches the value stored in the alarm minute register, and the hour counter matches the value stored in the alarm hour register, the alarm flag (ALMF) will be set. A CPU interrupt request is generated if the alarm interrupt enable bit (ALMIE) is also set. 12.5.4 Chronograph Functions The chronograph function is provided by a counter clocked at 128Hz (CGMXCLK/256). This counter can be started, stopped, and cleared at any time. The value of this chronograph counter is converted to 100Hz resolution and stored in the chronograph data register. Hence, the value in the chronograph register counts from 0 to 99 (and rolls over), with each increment representing 1/100th of a second (10ms). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 223 Real Time Clock (RTC) The value in the chronograph data register satisfies the following equation: (128Hz counter value x 25) + 16 ------------------------------------------------------------------------------------32 The accuracy of the chronograph counter is 5ms (max). 12.5.5 Timebase Interrupts In addition to the second, minute, hour, and day periodic interrupts generated by the clock functions, the divider circuits generates four periodic clocks, separated into two groups: 2Hz and 4Hz; 8Hz and 16Hz. The TBH bit in the RTC control register 2 (RTCCR2) selects the group for the timebase interrupts, indicated by TB1F and TB2F flags. A CPU interrupt request is generated if the corresponding enable bits (TB1IE and TB2IE) are also set. 12.6 RTC Interrupts The RTC has one alarm interrupt and seven periodic interrupts: * * Alarm interrupt Periodic interrupts: - Second - Minute - Hour - Day - 1/128 seconds (chronograph) - Timebase 1 and 2: 1/2 seconds and 1/4 seconds, or 1/8 seconds and 1/16 seconds A CPU interrupt request is generated if the corresponding interrupt enable bits are also set. Data Sheet 224 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Clock Calibration and Compensation 12.7 RTC Clock Calibration and Compensation The RTC module is built with a calibration and compensation circuit for the CGMXCLK. The circuit is used to compensate frequency errors of the 32.768kHz crystal so that a more accurate 1-Hz RTC clock can be achieved. Using this method, it is possible to use a less expensive crystal. If the crystal temperature profile and the current temperature is known, the calibration circuit can also be used to compensate crystal frequency errors due to ambient temperature change and crystal aging. The circuit provides a 60ppm compensation range, which is suitable for common 30ppm crystals, and can achieve a compensated RTC clock accuracy between -3ppm and +2ppm. CALIN 1-Hz REF / 30 tdiff CGMXCLK (32.768-kHz) / 983040 EVOL / 32766 / 32767 / 32768 / 32769 / 32770 COMPENSATED 1-Hz E-REGISTER 1-Hz FROM CGMXCLK / 32768 A B1 1-Hz RTC CLOCK S COMEN Figure 12-3. RTC Clock Calibration and Compensation The automatic calibration process works by comparing an external 1-Hz (1ppm) signal driven into the CALIN pin, with the CGMXCLK signal driven by the 32.768kHz crystal. The calibration is started by setting the CAL bit followed by the AUTOCAL bit in the RTC calibration register (RTCCOMR). During calibration, the tdiff block compares the time difference between the two clock sources for 15 seconds. This time difference is expressed in the number of CGMXCLK clock cycles and stored in two's complement format in the 6-bit E-register (the RTC calibration data register, RTCCDAT). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 225 Real Time Clock (RTC) A negative E-value indicates the number of CGMXCLK cycles that needs to be subtracted, because the CGMXCLK is slower than the ideal 32.768kHz; 32768 CGMXCLK cycles will be more longer than 1-second. A positive E-value indicates the number of CGMXCLK cycles that needs to be added, because the CGMXCLK is faster than the ideal 32.768kHz; 32768 CGMXCLK cycles will be more shorter than 1-second. If the time difference is more than 31 CGMXCLK cycles, the E-register will overflow, causing the EVOL flag to be set. The maximum (+30) or minimum (-30) value will remain in the E-register. After calibration, with the E-value stored in the calibration data register, clock compensation is only enabled when the COMEN bit is set in RTCCR2. As the E-value is the time difference for 15 seconds, the CGMXCLK is modified for every 15-second intervals. The CGMXCLK additions and subtractions are simulated using programmable dividers, therefore, the compensated clock does not have the same period within the 15-second, but is consistent for every 15-second periods. See Table 12-2 and Figure 12-4. 12.7.1 Calibration Error During clock calibration, the reference signal to the CALIN pin is not synchronized to the CGMXCLK being measured. A maximum inaccuracy of minus 1.5xCGMXCLK period or plus 1xCGMXCLK period will be introduced to the time difference measured. Table 12-2. Compensation Algorithm for Different Values of E Period A E -30 E -16 -15 E -1 E =0 1 E 15 16 E 30 Number of CGMXCLK Cycles (|E| - 15) x 32766 |E| x 32767 CGMXCLK Divider A 32766 32767 Period B Number of CGMXCLK Cycles (30 - |E|) x 32767 (15 - |E|) x 32768 CGMXCLK Divider B 32767 32768 No compensation is required: Divider is 32768 throughout. |E| x 32769 (|E| - 15) x 32770 32769 32770 (15 - |E|) x 32768 (30 - |E|) x 32769 32769 32769 Data Sheet 226 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Register and Bit Write Protection TRUE 15 SECONDS CGMXCLK UNCOMPENSATED 1-Hz CLOCK (CGMXCLK / 32768) COMPENSATED 1-Hz CLOCK PERIOD A 1-Hz CLOCK = CGMXCLK / A PERIOD B 1-Hz CLOCK = CGMXCLK / B Figure 12-4. 1-Hz Clock Compensation 12.8 RTC Register and Bit Write Protection A write-protect mechanism is implemented to prevent accidental writes to the RTC clock registers, calendar registers, and other control bits. The protected RTC registers and bits are listed in Table 12-3. Table 12-3. Write-Protected RTC Registers and Bits Register Bit CAL RTC Control Register 1 AUTOCAL OUTF[1:0] COMEN RTC Control Register 2 RTCE Second Register Minute Register Hour Register Day-Of-Week Register Day Register Month Register Year Register (All Bits) (All Bits) (All Bits) (All Bits) (All Bits) (All Bits) (All Bits) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 227 Real Time Clock (RTC) The mechanism uses the RTCWE[1:0] bits in the RTC calibration control register (RTCCOMR) in a state machine, which requires a bit-write sequence to disable the write-protection. A block diagram of the state machine is shown in Figure 12-5. R ESET Write-Protect ENABLED Write-Protect DISABLED Write any value other than 10 to RTWE Write 10 W rite 10 to E CW RT to RTCW E Note: Reading RTCWE[1:0] always return 00. RTCWE = 00 Write any value other than 00 to RTWE Write than 1 e other any valu CWE 0 to RT RTCWE = 10 Write 11 to Write 0 to te 0 Wri RTC r othe alue ny v TCWE R te a Wri 01 to than any valu e oth RTCWE er th a n 11 to R TCW E RTCWE = 11 TC WE Figure 12-5. RTC Write Protect State Diagram After a reset, the write-protect mechanism is disabled, allowing the user code to calibrate the RTC clock, set the time in the clock registers, and set the date in the calendar registers. To enable write-protect after reset or write-protect is disabled execute the following code: RTCWE1 EQU RTCWE0 EQU 1 0 ;RTCWE1 bit ;RTCWE0 bit WE R 1 to te 0 i Wr RTCWE 01 Data Sheet 228 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Low-Power Modes RTCWE_R EQU $40 ... RTC_WRTIE_PROTECT ... ;RTCCOMR register BSET BSET RTCWE1,RTCWE_R ;write %10 RTCWE1,RTCWE_R ;write %10 again To disable write-protect after write-protect is enabled execute the following code: RTCWE1 EQU 1 RTCWE0 EQU 0 RTCWE_R EQU $40 ... RTC_WRITE_ENABLE ... BCLR BSET LDA ORA STA BSET RTCWE1,RTCWE_R RTCWE0,RTCWE_R RTCWE_R #%00000011 RTCWE_R RTCWE1,RTCWE_R ;write %00 ;write %01 ;RTCWE1 bit ;RTCWE0 bit ;RTCCOMR register BSET BSET RTCWE1,RTCWE_R ;write %10 twice to RTCWE1,RTCWE_R ;ensure protected ;write %11 ;write %10 ... ; Write-protect is disabled, RTC registers/bits can be written. ... ; Protect register/bits again after write access. RTC_WRTIE_PROTECT BSET RTCWE1,RTCWE_R ;write %10 BSET RTCWE1,RTCWE_R ;write %10 again ... 12.9 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 12.9.1 Wait Mode The RTC module continues normal operation in wait mode. Any enabled CPU interrupt request from the RTC can bring the MCU out of wait mode. If the RTC is not required to bring the MCU out of wait mode, power down the RTC by clearing the RTCE bit before executing the WAIT instruction. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 229 Real Time Clock (RTC) 12.9.2 Stop Mode For continuous RTC operation in stop mode, the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XCLKEN is set, CGMXCLK continues to drive the RTC module, and any enabled CPU interrupt request from the RTC can bring the MCU out of stop mode. If STOP_XCLKEN bit is cleared, the RTC module is inactive after the execution of a STOP instruction. The STOP instruction does not affect RTC register states. RTC module operation resumes after an external interrupt. To further reduce power consumption, the RTC module should be powered-down by clearing the RTCE bit before executing the STOP instruction. 12.10 RTC Registers The RTC module has fifteen memory-mapped registers: * * * * * * * * * * * * * * RTC calibration control register (RTCCOMR) RTC calibration data register (RTCCDAT) RTC control register 1 (RTCCR1) RTC control register 2 (RTCCR2) RTC status register (RTCSR) Alarm minute and hour registers (ALMR and ALHR) Second register (SECR) Minute register (MINR) Hour register (HRR) Day register (DAY) Month register (MTHR) Year register (YRR) Day of the week register (DOWR) Chronograph data register (CHRR) Data Sheet 230 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers 12.10.1 RTC Calibration Control Register (RTCCOMR) The RTC calibration control register (RTCCOMR) contains control bits for RTC calibration, output option for the CALOUT pin, and registers/bits write-protect enable. Address: Read: Write: Reset: $0040 0 R 0 0 R 0 CAL* 0 AUTOCAL* OUTF1* 0 OUTF0* 0 0 0 RTCWE1 RTCWE0 0 0 0 * CAL, AUTOCAL, and OUTF{1:0] bits are write-protected; unprotect by a write sequence to RTCWE[1:0]. Figure 12-6. RTC Calibration Control Register (RTCCOMR) CAL -- RTC Calibration Mode This read/write bit enables the RTC calibration circuit. The CAL bit is cleared automatically after completion of automatic calibration if AUTOCAL is also set when CAL bit is set. 1 = RTC calibration mode enabled 0 = RTC calibration mode disabled AUTOCAL -- RTC Automatic Calibration Enable This read/write bit enables the CALIN pin to accept an incoming 1-Hz signal and calibration circuits for RTC automatic calibration. This bit can only be set when the CAL bit is set. After calibration (approx. 15 seconds), the AUTOCAL bit is automatically cleared. 1 = RTC automatic calibration enabled 0 = RTC automatic calibration disabled NOTE: RTC clock and calendar functions are not affected when calibration is enabled. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 231 Real Time Clock (RTC) OUTF[1:0] -- Calibration Mode CALOUT Pin Output Selection These two bits select the output option for the CALOUT pin. When CAL = 0, OUTF[1:0] is always 00. Table 12-4. CALOUT Pin Output Option OUTF[1:0] 00 01 10 11 CALOUT Pin Output CALOUT pin is disconnected. CALOUT pin outputs compensated 1-Hz. CALOUT pin outputs CGMXCLK clock. Reserved RTCWE[1:0] -- RTC Module Write Enable These two write-only bits control the write-protect function of several RTC registers and bits. After a reset, write-protect is disabled, allowing full write access to RTC registers and bits. These two bits always read as 0. To enable write-protect, perform the following sequence: 1. Write %10 to RTCWE[1:0] bits 2. Write %10 to RTCWE[1:0] bits To disable write-protect, perform the following sequence: 1. Write %00 to RTCWE[1:0] bits 2. Write %01 to RTCWE[1:0] bits 3. Write %11 to RTCWE[1:0] bits 4. Write %10 to RTCWE[1:0] bits To disable write-protect from an unsure protection state, first perform the enable write-protect sequence, followed by the disable writeprotect sequence. Data Sheet 232 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers 12.10.2 RTC Calibration Data Register (RTCCDAT) The RTC calibration data register (RTCCDAT) contains the RTC calibration data. Address: Read: Write: Reset: U 0 $0041 EOVL 0 E5 U E4 U E3 U E2 U E1 U E0 U Figure 12-7. RTC Calibration Data Register (RTCCDAT) EOVL -- E Register Overflow This read-only bit indicates that the time difference recorded between CALIN and CGMXCLK after 15 seconds during the last automatic calibration had exceeded 31 CGMXCLK cycles. Clear this flag by writing to the E register after the CAL bit is set. Setting the AUTOCAL bit will also clear this flag, but subsequent automatic calibration may set this flag again. 1 = E register overflow detected during the last automatic calibration 0 = No E register overflow detected during last automatic calibration E[5:0] -- RTC Compensation Value (E register) E[5:0] is a two's complement number which indicates the number of CGMXCLK cycles the RTC requires to compensate for a 15 second duration. If the compensation exceeds the limit of 31 CGMXCLK cycles, the E[5:0] bits remain at the maximum value of -30 (%100010) or +30 (%011110), and the EOVL flag will be set. When compensation is enabled (COMEN = 1): If E is negative, an E number of cycles will be subtracted from the 491520 CGMXCLK cycles (32768 x 15). When compensation is enabled (COMEN = 1): If E is positive, an E number of cycles will be added to the 491520 CGMXCLK cycles (32768 x 15). E[5:0] is written by the RTC compensation circuit during automatic calibration (AUTOCAL = 1). User can only write to E{5:0] when AUTOCAL = 0 and CAL = 1. Reset has no effect on E[1:0] bits. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 233 Real Time Clock (RTC) 12.10.3 RTC Control Register 1 (RTCCR1) The RTC control register 1 (RTCCR1) contains the eight interrupt enable bits for RTC interrupt functions. Address: Read: Write: Reset: $0042 ALMIE 0 CHRIE 0 DAYIE 0 HRIE 0 MINIE 0 SECIE 0 TB1IE 0 TB2IE 0 Figure 12-8. RTC Control Register 1 (RTCCR1) ALMIE -- Alarm Interrupt Enable This read/write bit enables the alarm flag, ALMF, to generate CPU interrupt requests. Reset clears the ALMIE bit. 1 = ALMF enabled to generate CPU interrupt 0 = ALMF not enabled to generate CPU interrupt CHRIE -- Chronograph Interrupt Enable This read/write bit enables the chronograph flag, CHRF, to generate CPU interrupt requests. Reset clears the CHRIE bit. 1 = CHRF enabled to generate CPU interrupt 0 = CHRF not enabled to generate CPU interrupt DAYIE -- Day Interrupt Enable This read/write bit enables the day flag, DAYF, to generate CPU interrupt requests. Reset clears the DAYIE bit. 1 = DAYF enabled to generate CPU interrupt 0 = DAYF not enabled to generate CPU interrupt HRIE -- Hour Interrupt Enable This read/write bit enables the hour flag, HRF, to generate CPU interrupt requests. Reset clears the HRIE bit. 1 = HRF enabled to generate CPU interrupt 0 = HRF not enabled to generate CPU interrupt MINIE -- Minute Interrupt Enable This read/write bit enables the minute flag, MINF, to generate CPU interrupt requests. Reset clears the MINIE bit. 1 = MINF enabled to generate CPU interrupt 0 = MINF not enabled to generate CPU interrupt Data Sheet 234 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers SECIE -- Second Interrupt Enable This read/write bit enables the second flag, SECF, to generate CPU interrupt requests. Reset clears the SECIE bit. 1 = SECF enabled to generate CPU interrupt 0 = SECF not enabled to generate CPU interrupt TB1IE -- Timebase 1 Interrupt Enable This read/write bit enables the timebase1 flag, TB1F, to generate CPU interrupt requests. Reset clears the TB1IE bit. 1 = TB1F enabled to generate CPU interrupt 0 = TB1F not enabled to generate CPU interrupt TB2IE -- Timebase 2 Interrupt Enable This read/write bit enables the timebase2 flag, TB2F, to generate CPU interrupt requests. Reset clears the TB2IE bit. 1 = TB2F enabled to generate CPU interrupt 0 = TB2F not enabled to generate CPU interrupt 12.10.4 RTC Control Register 2 (RTCCR2) The RTC control register 2 (RTCCR2) contains control and clock selection bits for RTC operation. Address: Read: Write: Reset: $0043 COMEN* U 0 CHRCLR 0 CHRE 0 RTCE* 0 TBH 0 0 0 0 0 0 0 = Unimplemented Reset by POR only. * COMEN and RTCE bits are write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-9. RTC Control Register 2 (RTCCR2) COMEN -- RTC Compensation Enable This read/write bit enables the clock compensation mechanism for CGMXCLK frequency errors. Reset has no effect on COMEN bit. 1 = Compensation mechanism enabled 0 = Compensation mechanism not enabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 235 Real Time Clock (RTC) NOTE: With compensation enabled, the RTC clock and calendar register updates may not be synchronized to the timebase and chronograph clocks, since their clocks are derived from the uncompensated CGMXCLK. Hence, time intervals for timebase ticks may not align with the RTC clock and calendar register updates. CHRCLR -- Chronograph counter clear Setting this write-only bit resets the chronograph counter and the chronograph data register (CHRR). Setting CHRCLR has no effect on any other registers. Counting resumes from $00. CHRCLR is cleared automatically after the chronograph counter is reset and always reads as logic 0. Reset clears the CHRCLR bit. 1 = Chronograph counter cleared 0 = No effect CHRE -- Chronograph Enable This read/write bit enables the chronograph counter. When the chronograph counter is disabled (CHRE = 0), the value in the chronograph data register is held at the count value. Reset clears the CHRE bit. 1 = Chronograph counter enabled 0 = Chronograph counter disabled RTCE -- Real Time Clock Enable This read/write bit enables the entire RTC module, allowing all RTC and chronograph operations. Disabling the RTC module does not affect the contents in the RTC registers. Reset clears the RTCE bit. 1 = RTC module enabled 0 = RTC module disabled TBH -- Timebase High Frequency Select This read/write bit selects the timebase interrupt period for TB1 and TB2. Reset clears the TBH bit. 1 = TB1 interrupt is 0.125s; TB2 interrupt is 0.0625s 0 = TB1 interrupt is 0.5s; TB2 interrupt is 0.25s Data Sheet 236 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers 12.10.5 RTC Status Register (RTCSR) The RTC status register contains eight status flags. When a flag is set and the corresponding interrupt enable bit is also set, a CPU interrupt request is generated. Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 $0044 ALMF CHRF DAYF HRF MINF SECF TB1F TB2F = Unimplemented Figure 12-10. RTC Status Register (RTCSR) ALMF -- Alarm Flag This clearable, read-only bit is set when the value in the RTC hour and minute counters matches the value in the alarm hour and alarm minute registers. When the ALMIE bit in RTCCR1 is set, ALMF generates a CPU interrupt request. In normal operation, clear the ALMF bit by reading RTCSR with ALMF set and then reading the alarm hour register (ALHR). Reset clears ALMF. 1 = RTC hour and minute counters matches the alarm hour and minute registers 0 = No matching between hour and minute counters and alarm hour and minute registers CHRF -- Chronograph Flag This clearable, read-only bit is set on every tick of the chronograph counter (every counter count). The tick is on every 1/128 seconds (see 12.5.4 Chronograph Functions). When the CHRIE bit in RTCCR1 is set, CHRF generates a CPU interrupt request. In normal operation, clear the CHRF bit by reading RTCSR with CHRF set and then reading the chronograph data register (CHRR). Reset clears CHRF. 1 = A chronograph counter tick has occurred 0 = No chronograph counter tick has occurred MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 237 Real Time Clock (RTC) DAYF -- Day Flag This clearable, read-only bit is set on every increment of the day counter. When the DAYIE bit in RTCCR1 is set, DAYF generates a CPU interrupt request. In normal operation, clear the DAYF bit by reading RTCSR with DAYF set and then reading the day register (DAYR). Reset clears DAYF. 1 = Day counter incremented 0 = No day counter incremented HRF -- Hour Flag This clearable, read-only bit is set on every increment of the hour counter. When the HRIE bit in RTCCR1 is set, HRF generates a CPU interrupt request. In normal operation, clear the HRF bit by reading RTCSR with HRF set and then reading the hour register (HRR). Reset clears HRF. 1 = Hour counter incremented 0 = No hour counter incremented MINF -- Minute Flag This clearable, read-only bit is set on every increment of the minute counter. When the MINIE bit in RTCCR1 is set, MINF generates a CPU interrupt request. In normal operation, clear the MINF bit by reading RTCSR with MINF set and then reading the minute register (MINR). Reset clears MINF. 1 = Minute counter incremented 0 = No minute counter incremented SECF -- Second Flag This clearable, read-only bit is set on every increment of the second counter. When the SECIE bit in RTCCR1 is set, SECF generates a CPU interrupt request. In normal operation, clear the SECF bit by reading RTCSR with SECF set and then reading the second register (SECR). Reset clears SECF. 1 = Second counter incremented 0 = No second counter incremented Data Sheet 238 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers TB1F -- Timebase 1 Flag This clearable, read-only bit is set on every tick of the timebase 1 counter (every 0.5 or 0.125 seconds). When the TB1IE bit in RTCCR1 is set, TB1F generates a CPU interrupt request. In normal operation, clear the TB1F bit by reading RTCSR with TB1F set and then reading the chronograph data register (CHRR). Reset clears TB1F. 1 = A timebase 1 tick has occurred 0 = No timebase 1 tick has occurred NOTE: Timebase 1 is not synchronized to the compensated RTC 1-Hz clock. Hence, time intervals for timebase ticks may not align with the RTC clock and calendar register updates. TB2F -- Timebase 2 Flag This clearable, read-only bit is set on every tick of the timebase 2 counter (every 0.25 or 0.0625 seconds). When the TB2IE bit in RTCCR1 is set, TB2F generates a CPU interrupt request. In normal operation, clear the TB2F bit by reading RTCSR with TB2F set and then reading the chronograph register (CHRR). Reset clears TB2F. 1 = A timebase 2 tick has occurred 0 = No timebase 2 tick has occurred NOTE: Timebase 2 is not synchronized to the compensated RTC 1-Hz clock. Hence, time intervals for timebase ticks may not align with the RTC clock and calendar register updates. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 239 Real Time Clock (RTC) 12.10.6 Alarm Minute and Hour Registers (ALMR and ALHR) These read/write registers contain the alarm minute and hour values for the hour and minute alarm function. When the hour counter matches the value in the alarm hour register (ALHR) and the minute counter matches the value in the alarm minute register (ALMR), the alarm flag, ALMF, is set. When ALMF is set and the alarm interrupt enable bit, ALMIE, is also set, a CPU interrupt request is generated. Address: Read: Write: Reset: 0 0 $0045 0 0 AM5 U AM4 U AM3 U AM2 U AM1 U AM0 U = Unimplemented Figure 12-11. Alarm Minute Register (ALMR) NOTE: Writing values other than 0 to 59, to ALMR is possible, but the alarm flag will never be set. Address: Read: Write: Reset: 0 0 0 $0046 0 0 0 AH4 U AH3 U AH2 U AH1 U AH0 U = Unimplemented Figure 12-12. Alarm Hour Register (ALHR) NOTE: Writing values other than 0 to 23, to ALHR is possible, but the alarm flag will never be set. Data Sheet 240 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers 12.10.7 Second Register (SECR) This read/write register contains the current value of the second counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the second counter and the counter continues to count from this new value. The second counter rolls over to 0 ($00) after reaching 59 ($4B). Writing a value other than 0 to 59 to this register has no effect. Address: Read: Write: Reset: 0 0 $0047 0 0 SEC5 U SEC4 U SEC3 U SEC2 U SEC1 U SEC0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-13. Second Register (SECR) 12.10.8 Minute Register (MINR) This read/write register contains the current value of the minute counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the minute counter and the counter continues to count from this new value. The minute counter rolls over to 0 ($00) after reaching 59 ($4B). Writing a value other than 0 to 59 to this register has no effect. Address: Read: Write: Reset: 0 0 $0048 0 0 MIN5 U MIN4 U MIN3 U MIN2 U MIN1 U MIN0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-14. Minute Register (MINR) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 241 Real Time Clock (RTC) 12.10.9 Hour Register (HRR) This read/write register contains the current value of the hour counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the hour counter and the counter continues to count from this new value. The hour counter rolls over to 0 ($00) after reaching 23 ($17). Writing a value other than 0 to 23 to this register has no effect. Address: Read: Write: Reset: 0 0 0 $0049 0 0 0 HR4 U HR3 U HR2 U HR1 U HR0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-15. Hour Register (HRR) 12.10.10 Day Register (DAYR) This read/write register contains the current value of the day-of-month counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the day counter and the counter continues to count from this new value. The day counter rolls over to 1 ($01) after reaching 28 ($1B), 29 ($1C), 30 ($1D), or 31 ($1E), depending on the value in the month and year registers. Writing a value that is not valid for the month and year to this register has no effect. Address: Read: Write: Reset: 0 0 0 $004A 0 0 0 DAY4 U DAY3 U DAY2 U DAY1 U DAY0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-16. Day Register (DAYR) Data Sheet 242 Real Time Clock (RTC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) RTC Registers 12.10.11 Month Register (MTHR) This read/write register contains the current value of the month counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the month counter and the counter continues to count from this new value. The month counter rolls over to 1 ($01) after reaching 12 ($0B). Writing a value other than 1 to 12 to this register has no effect. Address: Read: Write: Reset: 0 0 0 0 $004B 0 0 0 0 MTH3 U MTH2 U MTH1 U MTH0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-17. Month Register (MTHR) 12.10.12 Year Register (YRR) This read/write register contains the current value of the year counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the year counter and the counter continues to count from this new value. The value stored in this register is a two's complement representation of the year, relative to 2000. For example, the year 2008 is represented by 8 ($08), and the year 1979 is presented by -11 ($F5). The range of this register is only valid for -99 to +99. Address: Read: Write: Reset: $004C YR7 U YR6 U YR5 U YR4 U YR3 U YR2 U YR1 U YR0 U This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-18. Year Register (YRR) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Real Time Clock (RTC) Data Sheet 243 Real Time Clock (RTC) 12.10.13 Day-Of-Week Register (DOWR) This read/write register contains the current value of the day-of-week counter. This register can be read at any time without affecting the counter count. Writing to this register loads the value to the day-of-week counter and the counter continues to count from this new value. The day-of-week counter value rolls over to 0 ($00) after reaching 6 ($06). Writing a value other than 0 to 6 to this register has no effect. Address: Read: Write: Reset: 0 0 0 0 0 $004D 0 0 0 0 0 DOW2 U DOW1 U DOW0 U = Unimplemented This register is write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR. Figure 12-19. Day-Of-Week Register (DOWR) 12.10.14 Chronograph Data Register (CHRR) This read-only chronograph data register contains the value in the chronograph counter. Reset clears the chronograph data register. Setting the chronograph counter reset bit (CHRCLR) also clears the chronograph data register. The chronograph data register has a resolution of 1/100 seconds. The chronograph counter value rolls over to $00 after reaching $63. Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 $004E 0 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0 = Unimplemented Figure 12-20. Chronograph Data Register (CHRR) NOTE: The chronograph counter is not synchronized to the compensated RTC 1-Hz clock. Hence, chronograph ticks may not align with the RTC clock and calendar register updates. MC68HC908LJ24/LK24 -- Rev. 2.1 Real Time Clock (RTC) Freescale Semiconductor Data Sheet 244 Data Sheet -- MC68HC908LJ24 Section 13. Infrared Serial Communications Interface Module (IRSCI) 13.1 Contents 13.2 13.3 13.4 13.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6 Infrared Functional Description. . . . . . . . . . . . . . . . . . . . . . . . 250 13.6.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.6.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.7 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .252 13.7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.7.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 13.7.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.7.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.7.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.7.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 13.7.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .257 13.7.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.7.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.7.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.7.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13.7.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 13.7.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .261 13.7.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13.7.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13.7.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 245 Infrared Serial Communications 13.9 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .267 13.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.1 PTB0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 13.11.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 13.11.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.11.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.11.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.11.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 13.11.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 13.11.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .282 13.11.8 SCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . . . . 285 13.2 Introduction This section describes the infrared serial communications interface (IRSCI) module which allows high-speed asynchronous communications with peripheral devices and other MCUs. This IRSCI consists of an SCI module for conventional SCI functions and a software programmable infrared encoder/decoder sub-module for encoding/decoding the serial data for connection to infrared LEDs in remote control applications. NOTE: References to DMA (direct-memory access) and associated functions are only valid if the MCU has a DMA module. This MCU does not have the DMA function. Any DMA-related register bits should be left in their reset state for normal MCU operation. Data Sheet 246 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Features 13.3 Features Features of the SCI module include the following: * * * * * * Full duplex operation Standard mark/space non-return-to-zero (NRZ) format Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup * Interrupt-driven operation with eight interrupt flags: - Transmitter empty - Transmission complete - Receiver full - Idle receiver input - Receiver overrun - Noise error - Framing error - Parity error * * * Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection Features of the infrared (IR) sub-module include the following: * * IR sub-module enable/disable for infrared SCI or conventional SCI on TxD and RxD pins Software selectable infrared modulation/demodulation (3/16, 1/16 or 1/32 width pulses) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 247 Infrared Serial Communications Addr. Register Name Bit 7 6 ENSCI 0 TCIE 0 T8 U TC 5 0 4 M 0 ILIE 0 DMATE 0 IDLE 3 WAKE 0 TE 0 ORIE 0 OR 2 ILTY 0 RE 0 NEIE 0 NF 1 PEN 0 RWU 0 FEIE 0 FE Bit 0 PTY 0 SBK 0 PEIE 0 PE $0013 Read: LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 Read: SCI Control Register 2 Write: (SCC2) Reset: Read: SCI Control Register 3 Write: (SCC3) Reset: Read: SCI Status Register 1 Write: (SCS1) Reset: Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: Read: SCI Infrared Control Register Write: (SCIRCR) Reset: SCTIE 0 R8 0 SCRIE 0 DMARE 0 SCRF $0014 $0015 U SCTE $0016 1 0 1 0 0 0 0 0 0 0 0 0 0 BKF 0 RPF $0017 0 R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 $0018 Unaffected by reset CKS 0 R 0 0 SCP1 0 0 SCP0 0 0 R 0 R 0 SCR2 0 TNP1 0 U = Unaffected SCR1 0 TNP0 0 SCR0 0 IREN 0 $0019 0 0 $001A 0 0 0 R = Reserved = Unimplemented Figure 13-1. IRSCI I/O Registers Summary Data Sheet 248 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Pin Name Conventions 13.4 Pin Name Conventions The generic names of the IRSCI I/O pins are: * * RxD (receive data) TxD (transmit data) IRSCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an IRSCI input or output reflects the name of the shared port pin. Table 13-1 shows the full names and the generic names of the IRSCI I/O pins. The generic pin names appear in the text of this section. Table 13-1. Pin Name Conventions Generic Pin Names: Full Pin Names: RxD PTB1/RxD TxD PTB0/TxD 13.5 IRSCI Module Overview The IRSCI consists of a serial communications interface (SCI) and a infrared interface sub-module as shown in Figure 13-2. INTERNAL BUS SCI_TxD CGMXCLK BUS CLOCK SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) SCI_R32XCLK SCI_R16XCLK SCI_RxD INFRARED SUB-MODULE TxD RxD Figure 13-2. IRSCI Block Diagram The SCI module provides serial data transmission and reception, with a programmable baud rate clock based on the bus clock or the CGMXCLK. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 249 Infrared Serial Communications The infrared sub-module receives two clock sources from the SCI module: SCI_R16XCLK and SCI_R32XCLK. Both reference clocks are used to generate the narrow pulses during data transmission. The SCI_R16XCLK and SCI_R32XCLK are internal clocks with frequencies that are 16 and 32 times the baud rate respectively. Both SCI_R16XCLK and SCI_R32XCLK clocks are used for transmitting data. The SCI_R16XCLK clock is used only for receiving data. NOTE: For proper SCI function (transmit or receive), the bus clock MUST be programmed to at least 32 times that of the selected baud rate. When the infrared sub-module is disabled, signals on the TxD and RxD pins pass through unchanged to the SCI module. 13.6 Infrared Functional Description Figure 13-3 shows the structure of the infrared sub-module. TNP[1:0] IREN SCI_TxD TRANSMIT ENCODER IR_TxD MUX TxD SCI_R32XCLK SCI_R16XCLK IR_RxD SCI_RxD MUX RECEIVE DECODER RxD Figure 13-3. Infrared Sub-Module Diagram The infrared sub-module provides the capability of transmitting narrow pulses to an infrared LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI module. The infrared submodule receives two clocks from the SCI. One of these two clocks is selected as the base clock to generate the 3/16, 1/16, or 1/32 bit width narrow pulses during transmission. Data Sheet 250 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Infrared Functional Description The sub-module consists of two main blocks: the transmit encoder and the receive decoder. When transmitting data, the SCI data stream is encoded by the infrared sub-module. For every "0" bit, a narrow "low" pulse is transmitted; no pulse is transmitted for "1" bits. When receiving data, the infrared pulses should be detected using an infrared photo diode for conversion to CMOS voltage levels before connecting to the RxD pin for the infrared decoder. The SCI data stream is reconstructed by stretching the "0" pulses. 13.6.1 Infrared Transmit Encoder The infrared transmit encoder converts the "0" bits in the serial data stream from the SCI module to narrow "low" pulses, to the TxD pin. The narrow pulse is sent with a duration of 1/32, 1/16, or 3/16 of a data bit width. When two consecutive zeros are sent, the two consecutive narrow pulses will be separated by a time equal to a data bit width. DATA BIT WIDTH DETERMINED BY BAUD RATE SCI DATA INFRARED SCI DATA PULSE WIDTH = 1/32, 1/16, OR 3/16 DATA BIT WIDTH Figure 13-4. Infrared SCI Data Example 13.6.2 Infrared Receive Decoder The infrared receive decoder converts low narrow pulses from the RxD pin to standard SCI data bits. The reference clock, SCI_R16XCLK, clocks a four bit internal counter which counts from 0 to 15. An incoming pulse starts the internal counter and a "0" is sent out to the IR_RxD output. Subsequent incoming pulses are ignored when the counter count is between 0 and 7; IR_RxD remains "0". Once the counter passes 7, an incoming pulse will reset the counter; IR_RxD remains "0". When the counter reaches 15, the IR_RxD output returns to "1", the counter stops and waits for further pulses. A pulse is interpreted as jitter if it arrives shortly after the counter reaches 15; IR_RxD remains "1". MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 251 Infrared Serial Communications 13.7 SCI Functional Description Figure 13-5 shows the structure of the SCI. INTERNAL BUS SCI DATA REGISTER TRANSMITTER INTERRUPT CONTROL DMA INTERRUPT CONTROL RECEIVE SHIFT REGISTER ERROR INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER SCI_RxD SCI_TxD SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL BKF RPF FLAG CONTROL M WAKE ILTY CGMXCLK BUS CLOCK A SL X B BAUD RATE GENERATOR PEN PTY DATA SELECTION CONTROL ENSCI R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE TRANSMIT CONTROL CKS ENSCI SL = 0 => X = A SL = 1 => X = B SCI_R32XCLK SCI_R16XCLK /16 Figure 13-5. SCI Module Block Diagram Data Sheet 252 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. NOTE: For SCI operations, the IR sub-module is transparent to the SCI module. Data at going out of the SCI transmitter and data going into the SCI receiver is always in SCI format. It makes no difference to the SCI module whether the IR sub-module is enabled or disabled. This SCI module is a standard HC08 SCI module with the following modifications: * * A control bit, CKS, is added to the SCI baud rate control register to select between two input clocks for baud rate clock generation The TXINV bit is removed from the SCI control register 1 NOTE: 13.7.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 13-6. 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY BIT BIT 7 STOP BIT NEXT START BIT START BIT 9-BIT DATA FORMAT BIT M IN SCC1 SET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY BIT BIT 8 STOP BIT NEXT START BIT Figure 13-6. SCI Data Formats MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 253 Infrared Serial Communications 13.7.2 Transmitter Figure 13-7 shows the structure of the SCI transmitter. The baud rate clock source for the SCI can be selected by the CKS bit, in the SCI baud rate register (see 13.11.7 SCI Baud Rate Register). CKS INTERNAL BUS CGMXCLK BUS CLOCK A SL X B SCP1 SCP0 SCR1 SCR2 SCR0 PRESCALER BAUD DIVIDER / 16 SCI DATA REGISTER SL = 0 => X = A SL = 1 => X = B 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 H START L STOP SCI_TxD TRANSMITTER CPU INTERRUPT REQUEST TRANSMITTER DMA SERVICE REQUEST M MSB SHIFT ENABLE PEN PTY PREAMBLE ALL 1s T8 DMATE DMATE SCTIE SCTE DMATE SCTE SCTIE TC TCIE TRANSMITTER CONTROL LOGIC SCTE LOOPS SCTIE TC TCIE ENSCI TE Figure 13-7. SCI Transmitter Data Sheet 254 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor BREAK ALL 0s SBK PARITY GENERATION LOAD FROM SCDR Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 13.7.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port pins. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 255 Infrared Serial Communications 13.7.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the SCI receiver full bit (SCRF) in SCS1 Clears the SCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 13.7.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. Data Sheet 256 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR. 13.7.2.5 Transmitter Interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: * SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. * 13.7.3 Receiver Figure 13-8 shows the structure of the SCI receiver. 13.7.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 257 Infrared Serial Communications INTERNAL BUS SCR1 CKS SCP1 SCP0 CGMXCLK BUS CLOCK A SL X B PRESCALER BAUD DIVIDER SCR2 SCR0 START 0 L RWU / 16 DATA RECOVERY ALL 0s ALL 1s MSB SCI DATA REGISTER SL = 0 => X = A SL = 1 => X = B 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 SCI_RxD BKF RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST CPU INTERRUPT REQUEST M WAKE ILTY PEN PTY WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE STOP H SCRF IDLE R8 ILIE SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE Figure 13-8. SCI Receiver Block Diagram Data Sheet 258 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 13.7.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 13-9): * * After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) START BIT LSB SCI_RxD SAMPLES START BIT QUALIFICATION START BIT VERIFICATION DATA SAMPLING RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT16 RT1 RT2 RT3 RT4 Figure 13-9. Receiver Data Sampling MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 259 Infrared Serial Communications To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-2 summarizes the results of the start bit verification samples. Table 13-2. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-3 summarizes the results of the data bit samples. Table 13-3. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 Data Sheet 260 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-4 summarizes the results of the stop bit samples. Table 13-4. Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 13.7.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. The FE flag is set at the same time that the SCRF bit is set. A break character that has no stop bit also sets the FE bit. 13.7.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 261 Infrared Serial Communications As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 13-10 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RT10 RT11 RT12 RT13 RT14 RT15 DATA SAMPLES Figure 13-10. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 13-10, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 - 147 x 100 = 4.54% ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 13-10, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. Data Sheet 262 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RECEIVER RT CLOCK Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 - 163 x 100 = 4.12% ------------------------170 Fast Data Tolerance Figure 13-11 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RT10 RT11 RT12 RT13 RT14 RT15 DATA SAMPLES Figure 13-11. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 13-11, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is * 154 - 160 x 100 = 3.90% ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 13-11, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 263 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RECEIVER RT CLOCK Infrared Serial Communications The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 - 176 x 100 = 3.53% ------------------------170 13.7.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: * Address mark -- An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. * NOTE: Clearing the WAKE bit after the RxD pin has been idle may cause the receiver to wake up immediately. Data Sheet 264 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI Functional Description 13.7.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: * SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests. * 13.7.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. Noise flag (NF) -- The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) -- The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. Data Sheet 265 * * * MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Infrared Serial Communications 13.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 13.8.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. Refer to 9.7 Low-Power Modes for information on exiting wait mode. 13.8.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. Refer to 9.7 Low-Power Modes for information on exiting stop mode. Data Sheet 266 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) SCI During Break Module Interrupts 13.9 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 13.10 I/O Signals The two IRSCI I/O pins are: * * PTB0/TxD -- Transmit data PTB1/RxD -- Receive data 13.10.1 PTB0/TxD (Transmit Data) The PTB0/TxD pin is the serial data (standard or infrared) output from the SCI transmitter. The IRSCI shares the PTB0/TxD pin with port B. When the IRSCI is enabled, the PTB0/TxD pin is an output regardless of the state of the DDRB0 bit in data direction register B (DDRB). TxD pin has high current (15mA) sink capability when the LEDB0 bit is set in the port B LED control register ($000C). 13.10.2 PTB1/RxD (Receive Data) The PTB1/RxD pin is the serial data input to the IRSCI receiver. The IRSCI shares the PTB1/RxD pin with port B. When the IRSCI is enabled, the PTB1/RxD pin is an input regardless of the state of the DDRB1 bit in data direction register B (DDRB). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 267 Infrared Serial Communications Table 13-5 shows a summary of I/O pin functions when the SCI is enabled. Table 13-5. SCI Pin Functions (Standard and Infrared) SCC1 [ENSCI] 1 1 1 1 1 1 1 1 0 SCIRCR [IREN] 0 0 0 0 1 1 1 1 X SCC2 [TE] 0 0 1 1 0 0 1 1 X SCC2 [RE] 0 1 0 1 0 1 0 1 X Hi-Z(1) Hi-Z(1) Output SCI (idle high) Output SCI (idle high) Hi-Z(1) Hi-Z(1) Output IR SCI (idle high) Output IR SCI (idle high) TxD Pin RxD Pin Input ignored (terminate externally) Input sampled, pin should idle high Input ignored (terminate externally) Input sampled, pin should idle high Input ignored (terminate externally) Input sampled, pin should idle high Input ignored (terminate externally) Input sampled, pin should idle high Pins under port control (standard I/O port) Notes: 1. After completion of transmission in progress. 13.11 I/O Registers The following I/O registers control and monitor SCI operation: * * * * * * * * SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR) SCI infrared control register (SCIRCR) Data Sheet 268 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.1 SCI Control Register 1 SCI control register 1: * * * * * * * * Address: Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type $0013 Bit 7 6 ENSCI 0 5 0 4 M 0 3 WAKE 0 2 ILTY 0 1 PEN 0 Bit 0 PTY 0 Read: Write: Reset: LOOPS 0 0 Figure 13-12. SCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit This read/write bit enables loop mode operation for the SCI only. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. The infrared encoder/decoder is not in the loop. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 269 Infrared Serial Communications M -- Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 13-6.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY -- Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 13-6.) When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 13-6.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled Data Sheet 270 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers PTY -- Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 13-6.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 13-6. Character Format Selection Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits 13.11.2 SCI Control Register 2 SCI control register 2: * Enables the following CPU interrupt requests: - Enables the SCTE bit to generate transmitter CPU interrupt requests - Enables the TC bit to generate transmitter CPU interrupt requests - Enables the SCRF bit to generate receiver CPU interrupt requests - Enables the IDLE bit to generate receiver CPU interrupt requests * * * * MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Enables the transmitter Enables the receiver Enables SCI wakeup Transmits SCI break characters Data Sheet 271 Infrared Serial Communications Address: $0014 Bit 7 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 Read: Write: Reset: SCTIE 0 Figure 13-13. SCI Control Register 2 (SCC2) SCTIE -- SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE -- SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition Data Sheet 272 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 273 Infrared Serial Communications 13.11.3 SCI Control Register 3 SCI control register 3: * * Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables the following interrupts: - Receiver overrun interrupts - Noise error interrupts - Framing error interrupts - Parity error interrupts Address: $0015 Bit 7 Read: Write: Reset: U R8 6 T8 U 5 DMARE 0 4 DMATE 0 3 ORIE 0 U = Unaffected 2 NEIE 0 1 FEIE 0 Bit 0 PEIE 0 = Unimplemented Figure 13-14. SCI Control Register 3 (SCC3) R8 -- Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. Data Sheet 274 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers DMARE -- DMA Receive Enable Bit CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) 0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI receiver CPU interrupt requests enabled) DMATE -- DMA Transfer Enable Bit CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance. 1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled 0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. Reset clears ORIE. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 275 Infrared Serial Communications PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. (See 13.11.4 SCI Status Register 1.) Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 13.11.4 SCI Status Register 1 SCI status register 1 contains flags to signal these conditions: * * * * * * * * Address: Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error $0016 Bit 7 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE Read: Write: Reset: SCTE 1 1 0 0 0 0 0 0 = Unimplemented Figure 13-15. SCI Status Register 1 (SCS1) SCTE -- SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal Data Sheet 276 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 277 Infrared Serial Communications OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 13-16 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flagclearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flagclearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected Data Sheet 278 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3 SCRF = 0 OR = 0 BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2 BYTE 3 DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 1 SCRF = 0 OR = 1 SCRF = 1 OR = 1 BYTE 3 BYTE 1 BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 Figure 13-16. Flag Clearing Sequence PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 279 Infrared Serial Communications 13.11.5 SCI Status Register 2 (SCS2) SCI status register 2 contains flags to signal the following conditions: * * Address: Break character detected Incoming data $0017 Bit 7 6 0 5 0 4 0 3 0 2 0 1 BKF Bit 0 RPF Read: Write: Reset: 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 13-17. SCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress Data Sheet 280 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Unaffected by reset Figure 13-18. SCI Data Register (SCDR) R7/T7-R0/T0 -- Receive/Transmit Data Bits Reading the SCDR accesses the read-only received data bits, R7-R0. Writing to the SCDR writes the data to be transmitted, T7-T0. Reset has no effect on the SCDR. NOTE: Do not use read/modify/write instructions on the SCI data register. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 281 Infrared Serial Communications 13.11.7 SCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 Read: Write: Reset: CKS 0 6 0 5 SCP1 0 4 SCP0 0 3 R 0 R 2 SCR2 0 = Reserved 1 SCR1 0 Bit 0 SCR0 0 0 = Unimplemented Figure 13-19. SCI Baud Rate Register (SCBR) CKS -- Baud Clock Input Select This read/write bit selects the source clock for the baud rate generator. Reset clears the CKS bit, selecting CGMXCLK. 1 = Bus clock drives the baud rate generator 0 = CGMXCLK drives the baud rate generator SCP1 and SCP0 -- SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 13-7. Reset clears SCP1 and SCP0. Table 13-7. SCI Baud Rate Prescaling SCP1 and SCP0 00 01 10 11 Prescaler Divisor (PD) 1 3 4 13 SCR2-SCR0 -- SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 13-8. Reset clears SCR2-SCR0. Data Sheet 282 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers Table 13-8. SCI Baud Rate Selection SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 Use this formula to calculate the SCI baud rate: SCI clock source baud rate = -------------------------------------------16 x PD x BD where: SCI clock source = fBUS or CGMXCLK (selected by CKS bit) PD = prescaler divisor BD = baud rate divisor Table 13-9 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when fBUS is selected as SCI clock source. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 283 Infrared Serial Communications Table 13-9. SCI Baud Rate Selection Examples SCP1 and SCP0 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (fBUS = 4.9152 MHz) -- -- 76800 38400 19200 9600 4800 2400 -- 51200 25600 12800 6400 3200 1600 800 76800 38400 19200 9600 4800 2400 1200 600 23632 11816 5908 2954 1477 739 369 185 Data Sheet 284 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) I/O Registers 13.11.8 SCI Infrared Control Register The infrared control register contains the control bits for the infrared submodule. * * Address: Enables the infrared sub-module Selects the infrared transmitter narrow pulse width $001A Bit 7 6 0 5 0 4 0 3 R 0 R 2 TNP1 0 = Reserved 1 TNP0 0 Bit 0 IREN 0 Read: Write: Reset: R 0 0 0 0 = Unimplemented Figure 13-20. SCI Infrared Control Register (SCIRCR) TNP1 and TNP0 -- Transmitter Narrow Pulse Bits These read/write bits select the infrared transmitter narrow pulse width as shown in Table 13-10. Reset clears TNP1 and TNP0. Table 13-10. Infrared Narrow Pulse Selection TNP1 and TNP0 00 01 10 SCI transmits a 1/32 narrow pulse 11 Prescaler Divisor (PD) SCI transmits a 3/16 narrow pulse SCI transmits a 1/16 narrow pulse IREN -- Infrared Enable Bit This read/write bit enables the infrared sub-module for encoding and decoding the SCI data stream. When this bit is clear, the infrared submodule is disabled. Reset clears the IREN bit. 1 = Infrared sub-module enabled 0 = Infrared sub-module disabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) Data Sheet 285 Infrared Serial Communications Data Sheet 286 MC68HC908LJ24/LK24 -- Rev. 2.1 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 14. Serial Peripheral Interface Module (SPI) 14.1 Contents 14.2 14.3 14.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Pin Name Conventions and I/O Register Addresses . . . . . . . 289 14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 14.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 14.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . 293 14.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . 294 14.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . 296 14.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 297 14.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 14.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 14.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 14.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . 309 14.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . 309 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 287 Serial Peripheral Interface Module (SPI) 14.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . 314 14.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14.2 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 14.3 Features Features of the SPI module include the following: * * * * * * * Full-duplex operation Master and slave modes Double-buffered operation with separate transmit and receive registers Four master mode frequencies (maximum = bus frequency / 2) Maximum slave mode frequency = bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) * * * Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired-OR mode Data Sheet 288 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Pin Name Conventions and I/O Register Addresses 14.4 Pin Name Conventions and I/O Register Addresses The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 14-1. The generic pin names appear in the text that follows. Table 14-1. Pin Name Conventions SPI Generic Pin Names: MISO MOSI SS SPSCK CGND VSS PTD0/SS PTD3/SPSCK/ Full SPI Pin Names: SPI PTD1/MISO PTD2/MOSI CALIN CALOUT NOTE: The SS and SPSCK pins are also shared with CALIN and CALOUT respectively. To avoid erratic behavior, these two pins should never be configured for use as SPI and RTC calibration simultaneously. Figure 14-1 summarizes the SPI I/O registers. = Addr. Register Name Read: SPI Control Register Write: (SPCR) Reset: Read: SPI Status and Control Register Write: (SPSCR) Reset: Read: SPI Data Register Write: (SPDR) Reset: Bit 7 SPRIE 0 SPRF 6 R 0 ERRIE 0 R6 T6 5 SPMSTR 1 OVRF 4 CPOL 0 MODF 3 CPHA 1 SPTE 2 SPWOM 0 MODFEN 0 R2 T2 1 SPE 0 SPR1 0 R1 T1 Bit 0 SPTIE 0 SPR0 0 R0 T0 $0010 $0011 0 R7 T7 0 R5 T5 0 R4 T4 1 R3 T3 $0012 Unaffected by reset = Unimplemented R = Reserved Figure 14-1. SPI I/O Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 289 Serial Peripheral Interface Module (SPI) 14.5 Functional Description Figure 14-2 shows the structure of the SPI module. INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT / 2 FROM SIM 7 /2 /8 CLOCK DIVIDER / 32 / 128 CLOCK SELECT MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS 6 SHIFT REGISTER 5 4 3 2 1 0 MISO SPMSTR SPE SPR1 SPR0 SPMSTR CPHA CPOL RESERVED TRANSMITTER CPU INTERRUPT REQUEST RESERVED RECEIVER/ERROR CPU INTERRUPT REQUEST SPI CONTROL MODFEN ERRIE SPTIE SPRIE R SPE SPRF SPTE OVRF MODF SPWOM Figure 14-2. SPI Module Block Diagram The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interruptdriven. The following paragraphs describe the operation of the SPI module. Data Sheet 290 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Functional Description 14.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 14.14.1 SPI Control Register.) Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. (See Figure 14-3.) MASTER MCU SLAVE MCU SHIFT REGISTER MISO MOSI SPSCK MISO MOSI SPSCK SS SHIFT REGISTER BAUD RATE GENERATOR SS VDD Figure 14-3. Full-Duplex Master-Slave Connections MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 291 Serial Peripheral Interface Module (SPI) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 14.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit. 14.5.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. (See 14.8.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. Data Sheet 292 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Transmission Formats When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See 14.6 Transmission Formats.) NOTE: SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge. 14.6 Transmission Formats During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiplemaster bus contention. 14.6.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 293 Serial Peripheral Interface Module (SPI) The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE). 14.6.2 Transmission Format When CPHA = 0 Figure 14-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 14.8.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave's SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 14-5. Data Sheet 294 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Transmission Formats SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE 1 2 3 4 5 6 7 8 MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB Figure 14-4. Transmission Format (CPHA = 0) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 14-5. CPHA/SS Timing When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 295 Serial Peripheral Interface Module (SPI) 14.6.3 Transmission Format When CPHA = 1 Figure 14-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 14.8.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE 1 2 3 4 5 6 7 8 MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB Figure 14-6. Transmission Format (CPHA = 1) Data Sheet 296 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Transmission Formats When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 14.6.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 14-7.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 14-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 297 Serial Peripheral Interface Module (SPI) WRITE TO SPDR BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER INITIATION DELAY MSB BIT 6 BIT 5 1 2 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK / 128; 128 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 2; 2 POSSIBLE START POINTS Figure 14-7. Transmission Start Delay (Master) Data Sheet 298 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Queuing Transmission Data 14.7 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 14-8 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0). WRITE TO SPDR SPTE SPSCK CPHA:CPOL = 1:0 MOSI SPRF READ SPSCR READ SPDR 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET. MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654 654321 654321 BYTE 1 BYTE 2 BYTE 3 4 6 7 7 CPU READS SPDR, CLEARING SPRF BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 9 11 12 1 2 3 5 8 10 Figure 14-8. SPRF/SPTE CPU Interrupt Timing The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 299 Serial Peripheral Interface Module (SPI) For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. 14.8 Error Conditions The following flags signal SPI error conditions: * Overflow (OVRF) -- Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. Mode fault error (MODF) -- The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. * 14.8.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7. (See Figure 14-4 and Figure 14-6.) If an overflow occurs, all data received after the overflow and before the OVRF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive data register before the overflow occurred can still be read. Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF Data Sheet 300 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Error Conditions interrupts share the same CPU interrupt vector. (See Figure 14-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 14-9 shows how it is possible to miss an overflow. The first part of Figure 14-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR are read. BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8 SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 2 5 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8 7 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST. Figure 14-9. Missed Read of Overflow Condition In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 14-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 301 Serial Peripheral Interface Module (SPI) BYTE 1 SPI RECEIVE COMPLETE SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 5 6 7 2 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 4 6 8 8 9 9 10 12 13 14 1 BYTE 2 5 BYTE 3 7 BYTE 4 11 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 14-10. Clearing SPRF When OVRF Interrupt Is Not Enabled 14.8.2 Mode Fault Error Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: * * The SS pin of a slave SPI goes high during a transmission The SS pin of a master SPI goes low at any time For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. Data Sheet 302 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Error Conditions MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 14-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: * * * * * If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. The SPE bit is cleared. The SPTE bit is set. The SPI state counter is cleared. The data direction register of the shared I/O port regains control of port drivers. NOTE: To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit. (See 14.6 Transmission Formats.) NOTE: Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave. When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 303 Serial Peripheral Interface Module (SPI) slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared. 14.9 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. Table 14-2. SPI Interrupts Flag SPTE Transmitter empty SPRF Receiver full OVRF Overflow MODF Mode fault Request SPI transmitter CPU interrupt request (DMAS = 0, SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request (DMAS = 0, SPRIE = 1) SPI receiver/error interrupt request (ERRIE = 1) SPI receiver/error interrupt request (ERRIE = 1) Data Sheet 304 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Interrupts Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, regardless of the state of the SPE bit. (See Figure 14-11.) The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests. NOT AVAILABLE SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST R NOT AVAILABLE SPRIE SPRF SPI RECEIVER/ERROR ERRIE MODF OVRF CPU INTERRUPT REQUEST Figure 14-11. SPI Interrupt Request Generation MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 305 Serial Peripheral Interface Module (SPI) The following sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. SPI transmitter empty (SPTE) -- The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request. * 14.10 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: * * * * * The SPTE flag is set. Any transmission currently in progress is aborted. The shift register is cleared. The SPI state counter is cleared, making it ready for a new complete transmission. All the SPI port logic is defaulted back to being general-purpose I/O. These items are reset only by a system reset: * * * All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. Data Sheet 306 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Low-Power Modes By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 14.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 14.11.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). (See 14.9 Interrupts.) 14.11.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 307 Serial Peripheral Interface Module (SPI) 14.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Section 9. System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. 14.13 I/O Signals The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are: * * * * * MISO -- Data received MOSI -- Data transmitted SPSCK -- Serial clock SS -- Slave select CGND -- Clock ground (internally connected to VSS) Data Sheet 308 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) I/O Signals The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 14.13.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multipleslave system, a logic 1 on the SS pin puts the MISO pin in a highimpedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port. 14.13.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmits serial data. In fullduplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 309 Serial Peripheral Interface Module (SPI) 14.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 14.13.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 14.6 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Figure 14-12. MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 14-12. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. (See 14.14.2 SPI Status and Control Register.) NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a highimpedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. MC68HC908LJ24/LK24 -- Rev. 2.1 Serial Peripheral Interface Module (SPI) Freescale Semiconductor Data Sheet 310 Serial Peripheral Interface Module (SPI) I/O Signals When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 14.8.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. (See Table 14-3.) Table 14-3. SPI Configuration SPE 0 1 1 1 SPMSTR X(1) 0 1 1 MODFEN X X 0 1 SPI Configuration Not enabled Slave Master without MODF Master with MODF State of SS Logic General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI Note 1. X = Don't care 14.13.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to VSS as shown in Table 14-1. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 311 Serial Peripheral Interface Module (SPI) 14.14 I/O Registers Three registers control and monitor SPI operation: * * * SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR) 14.14.1 SPI Control Register The SPI control register: * * * * * Enables SPI module interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module Address: $0010 Bit 7 Read: Write: Reset: SPRIE 0 6 R 0 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 R 2 SPWOM 0 = Reserved 1 SPE 0 Bit 0 SPTIE 0 = Unimplemented Figure 14-13. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled Data Sheet 312 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) I/O Registers SPMSTR -- SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 14-4 and Figure 14-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA -- Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 14-4 and Figure 14-6.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 14-12.) Reset sets the CPHA bit. SPWOM -- SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 14.10 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 313 Serial Peripheral Interface Module (SPI) 14.14.2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions: * * * * Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty The SPI status and control register also contains bits that perform these functions: * * * Enable error interrupts Enable mode fault error detection Select master SPI baud rate Address: $0011 Bit 7 Read: Write: Reset: 0 SPRF 6 ERRIE 0 5 OVRF 4 MODF 3 SPTE 2 MODFEN 0 1 SPR1 0 Bit 0 SPR0 0 0 0 1 = Unimplemented Figure 14-14. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full Data Sheet 314 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) I/O Registers ERRIE -- Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit. 1 = Overflow 0 = No overflow MODF -- Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also. NOTE: Do not write to the SPI data register unless the SPTE bit is high. During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 315 Serial Peripheral Interface Module (SPI) MODFEN -- Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a generalpurpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See 14.13.4 SS (Slave Select).) If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See 14.8.2 Mode Fault Error.) SPR1 and SPR0 -- SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 14-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 14-4. SPI Master Baud Rate Selection SPR1 and SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = ------------------------2 x BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor Data Sheet 316 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) I/O Registers 14.14.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. (See Figure 14-2.) Address: $0012 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Unaffected by reset Figure 14-15. SPI Data Register (SPDR) R7-R0/T7-T0 -- Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Serial Peripheral Interface Module (SPI) Data Sheet 317 Serial Peripheral Interface Module (SPI) Data Sheet 318 Serial Peripheral Interface Module (SPI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 15. Multi-Master IIC Interface (MMIIC) 15.1 Contents 15.2 15.3 15.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 15.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . 321 15.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . 323 15.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . . 324 15.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . 326 15.5.5 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . 328 15.5.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . 329 15.6 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.2 Introduction This Multi-master IIC (MMIIC) Interface is designed for internal serial communication between the MCU and other IIC devices. A hardware circuit generates "start" and "stop" signal, while byte by byte data transfer is interrupt driven by the software algorithm. Therefore, it can greatly help the software in dealing with other devices to have higher system efficiency in a typical digital monitor system. This module not only can be applied in internal communications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. It also provides the flexibility of hooking additional devices to an existing system for future expansion without adding extra hardware. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 319 Multi-Master IIC Interface (MMIIC) This Multi-master IIC module uses the SCL clock line and the SDA data line to communicate with external DDC host or IIC interface. These two pins are shared with port pins PTD6/KBI6 and PTD7/KBI7 respectively. The outputs of SCL and SDA pins are open-drain type -- no clamping diode is connected between the pin and internal VDD. The maximum data rate typically is 750k-bps. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF. 15.3 Features * * * * * * * * * * Compatibility with multi-master IIC bus standard Software controllable acknowledge bit generation Interrupt driven byte by byte data transfer Calling address identification interrupt Auto detection of R/W bit and switching of transmit or receive mode Detection of START, repeated START, and STOP signals Auto generation of START and STOP condition in master mode Arbitration loss detection and No-ACK awareness in master mode 8 selectable baud rate master clocks Automatic recognition of the received acknowledge bit 15.4 I/O Pins The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O pins are listed in Table 15-1. The generic pin name appear in the text that follows. Table 15-1. Pin Name Conventions MMIIC Generic Pin Names: SDA SCL Full MCU Pin Names: PTD7/KBI7/SDA (1) PTD6/KBI6/SCL (1) Pin Selected for IIC Function By: MMEN bit in MMCR ($006C) MMEN bit in MMCR ($006C) Notes: 1. Do not enable the MMIIC function if the pin is used for KBI. Data Sheet 320 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers Addr. $006A Register Name Bit 7 6 5 MMBB 0 MMAD5 1 0 0 4 MMAST 0 MMAD4 0 0 0 3 MMRW 0 MMAD3 0 2 MMBR2 0 MMAD2 0 1 MMBR1 0 Bit 0 MMBR0 0 Read: MMALIF MMNAKIF Multi-Master IIC Master Control Register Write: 0 0 (MIMCR) Reset: 0 0 Read: Multi-Master IIC Address MMAD7 Register Write: (MMADR) Reset: 1 Read: Multi-Master IIC Control Register Write: (MMCR) Reset: MMEN 0 MMAD6 0 MMIEN 0 0 0 MMTD6 1 MMRD6 0 $006B MMAD1 MMEXTAD 0 0 0 0 0 0 $006C MMTXAK REPSEN 0 0 0 0 MMTD2 1 MMRD2 0 $006D Read: MMRXIF Multi-Master IIC 0 Status Register Write: (MMSR) Reset: 0 Read: Multi-Master IIC MMTD7 Data Transmit Register Write: (MMDTR) Reset: 1 Multi-Master IIC Read: MMRD7 Data Receive Register Write: (MMDRR) Reset: 0 MMTXIF MMATCH MMSRW MMRXAK 0 MMTD5 1 MMRD5 0 0 MMTD4 1 MMRD4 0 1 MMTD3 1 MMRD3 0 MMTXBE MMRXBF 1 MMTD1 1 MMRD1 0 0 MMTD0 1 MMRD0 0 $006E $006F = Unimplemented Figure 15-1. MMIIC I/O Register Summary 15.5 Multi-Master IIC Registers Six registers are associated with the Multi-master IIC module, they are outlined in the following sections. 15.5.1 Multi-Master IIC Address Register (MMADR) Address: $006B Bit 7 Read: Write: Reset: MMAD7 1 6 MMAD6 0 5 MMAD5 1 4 MMAD4 0 3 MMAD3 0 2 MMAD2 0 1 Bit 0 MMAD1 MMEXTAD 0 0 Figure 15-2. Multi-Master IIC Address Register (MMADR) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 321 Multi-Master IIC Interface (MMIIC) MMAD[7:1] -- Multi-Master Address These seven bits represent the MMIIC interface's own specific slave address when in slave mode, and the calling address when in master mode. Software must update MMAD[7:1] as the calling address while entering master mode and restore its own slave address after master mode is relinquished. This register is cleared as $A0 upon reset. MMEXTAD -- Multi-Master Expanded Address This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will acknowledge the following addresses from a calling master: $MMAD[7:1], 0000000, and 0001100. Reset clears this bit. 1 = MMIIC responds to the following calling addresses: $MMAD[7:1], 0000000, and 0001100. 0 = MMIIC responds to address $MMAD[7:1] For example, when MMADR is configured as: MMAD7 1 MMAD6 1 MMAD5 0 MMAD4 1 MMAD3 0 MMAD2 1 MMAD1 MMEXTAD 0 1 The MMIIC module will respond to the calling address: Bit 7 1 6 1 5 0 4 1 3 0 2 1 Bit 1 0 or the general calling address: 0 0 0 0 0 0 0 or the calling address: 0 0 0 1 1 0 0 NOTE: bit-0 of the 8-bit calling address is the MMRW bit from the calling master. Data Sheet 322 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers 15.5.2 Multi-Master IIC Control Register (MMCR) Address: $006C Bit 7 Read: Write: Reset: MMEN 0 6 MMIEN 0 5 0 4 0 3 2 1 0 Bit 0 0 MMTXAK REPSEN 0 0 0 0 0 0 = Unimplemented Figure 15-3. Multi-Master IIC Control Register (MMCR) MMEN -- Multi-Master IIC Enable This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags will restore to its poweron default states. Reset clears this bit. 1 = MMIIC module enabled 0 = MMIIC module disabled MMIEN -- Multi-Master IIC Interrupt Enable When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF flags are enabled to generate an interrupt request to the CPU. When MMIEN is cleared, the these flags are prevented from generating an interrupt request. Reset clears this bit. 1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU 0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not generate interrupt request to CPU MMTXAK -- Transmit Acknowledge Enable This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th clock bit. Reset clears this bit. 1 = MMIIC does not send acknowledge signals at 9th clock bit 0 = MMIIC sends acknowledge signal at 9th clock bit MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 323 Multi-Master IIC Interface (MMIIC) REPSEN -- Repeated Start Enable This bit is set to enable repeated START signal to be generated when in master mode transfer (MMAST = 1). The REPSEN bit is cleared by hardware after the completion of repeated START signal or when the MMAST bit is cleared. Reset clears this bit. 1 = Repeated START signal will be generated if MMAST bit is set 0 = No repeated START signal will be generated 15.5.3 Multi-Master IIC Master Control Register (MIMCR) Address: $006A Bit 7 6 5 MMBB 4 MMAST 0 3 MMRW 0 2 MMBR2 0 1 MMBR1 0 Bit 0 MMBR0 0 Read: MMALIF MMNAKIF Write: Reset: 0 0 0 0 0 = Unimplemented Figure 15-4. Multi-Master IIC Master Control Register (MIMCR) MMALIF -- Multi-Master Arbitration Lost Interrupt Flag This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA line in master mode - an arbitration loss. This bit generates an interrupt request to the CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = Lost arbitration in master mode 0 = No arbitration lost MMNAKIF -- No Acknowledge Interrupt Flag This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset. 1 = No acknowledge bit detected 0 = Acknowledge bit detected Data Sheet 324 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers MMBB -- Bus Busy Flag This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus idle) is detected. Reset clears this bit. 1 = Start condition detected 0 = Stop condition detected or MMIIC is disabled MMAST -- Master Control Bit This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR. When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module generates the stop condition to the lines after the current byte is transmitted. If an arbitration loss occurs (MMALIF = 1), the module reverts to slave mode by clearing MMAST, and releasing SDA and SCL lines immediately. This bit is cleared by writing "0" to it or by reset. 1 = Master mode operation 0 = Slave mode operation MMRW -- Master Read/Write This bit will be transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit. 1 = Master mode receive 0 = Master mode transmit MMBR2-MMBR0 -- Baud Rate Select These three bits select one of eight clock rates as the master clock when the module is in master mode. Since this master clock is derived the CPU bus clock, the user program should not execute the WAIT instruction when the MMIIC module in master mode. This will cause the SDA and SCL lines to hang, as the WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared upon reset. (See Table 15-2 . Baud Rate Select.) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 325 Multi-Master IIC Interface (MMIIC) Table 15-2. Baud Rate Select MMBR2 0 0 0 0 1 1 1 1 MMBR1 0 0 1 1 0 0 1 1 MMBR0 0 1 0 1 0 1 0 1 Baud Rate Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 Internal bus clock / 128 Internal bus clock / 256 Internal bus clock / 512 Internal bus clock / 1024 15.5.4 Multi-Master IIC Status Register (MMSR) Address: $006D Bit 7 Read: MMRXIF Write: Reset: 0 0 6 5 4 3 2 0 1 Bit 0 MMTXIF MMATCH MMSRW MMRXAK 0 0 0 0 1 MMTXBE MMRXBF 0 1 0 = Unimplemented Figure 15-5. Multi-Master IIC Status Register (MMSR) MMRXIF -- Multi-Master IIC Receive Interrupt Flag This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset; or when the MMEN = 0. 1 = New data in data receive register (MMDRR) 0 = No data received Data Sheet 326 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers MMTXIF -- Multi-Master Transmit Interrupt Flag This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit, and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0. 1 = Data transfer completed 0 = Data transfer in progress MMATCH -- Multi-Master Address Match This flag is set when the received data in the data receive register (MMDRR) is an calling address which matches with the address or its extended addresses (MMEXTAD=1) specified in the MMADR register. 1 = Received address matches MMADR 0 = Received address does not match MMSRW -- Multi-Master Slave Read/Write This bit indicates the data direction when the module is in slave mode. It is updated after the calling address is received from a master device. MMSRW = 1 when the calling master is reading data from the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive mode). 1 = Slave mode transmit 0 = Slave mode receive MMRXAK -- Multi-Master Receive Acknowledge When this bit is cleared, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has been detected at the 9th clock; the module will release the SDA line for the master to generate "stop" or "repeated start" condition. Reset sets this bit. 1 = No acknowledge signal received at 9th clock bit 0 = Acknowledge signal received at 9th clock bit MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 327 Multi-Master IIC Interface (MMIIC) MMTXBE -- Multi-Master Transmit Buffer Empty This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer of its data to the output circuit. Reset sets this bit. 1 = Data transmit register empty 0 = Data transmit register full MMRXBF -- Multi-Master Receive Buffer Full This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data from the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer of data from the input circuit to the MMDRR. Reset clears this bit. 1 = Data receive register full 0 = Data receive register empty 15.5.5 Multi-Master IIC Data Transmit Register (MMDTR) Address: $006E Bit 7 Read: Write: Reset: MMTD7 1 6 MMTD6 1 5 MMTD5 1 4 MMTD4 1 3 MMTD3 1 2 MMTD2 1 1 MMTD1 1 Bit 0 MMTD0 1 Figure 15-6. Multi-Master IIC Data Transmit Register (MMDTR) When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether module is in master or slave mode. In slave mode, the data in MMDTR will be transferred to the output circuit when: * * the module detects a matched calling address (MMATCH = 1), with the calling master requesting data (MMSRW = 1); or the previous data in the output circuit has be transmitted and the receiving master returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). Data Sheet 328 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Multi-Master IIC Registers If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (MMTXBE = 0). In master mode, the data in MMDTR will be transferred to the output circuit when: * the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). * If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (MMTXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 15-8. 15.5.6 Multi-Master IIC Data Receive Register (MMDRR) Address: $006F Bit 7 Read: MMRD7 Write: Reset: 0 0 0 0 0 0 0 0 6 MMRD6 5 MMRD5 4 MMRD4 3 MMRD3 2 MMRD2 1 MMRD1 Bit 0 MMRD0 = Unimplemented Figure 15-7. Multi-Master IIC Data Receive Register (MMDRR) When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether module is in master or slave mode. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 329 Multi-Master IIC Interface (MMIIC) In slave mode, the data in MMDRR is: * * the calling address from the master when the address match flag is set (MMATCH = 1); or the last data received when MMATCH = 0. In master mode, the data in the MMDRR is: * the last data received. When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF interrupt flag is set, indicating that new data is available in MMDRR. The sequence of events for slave receive and master receive are illustrated in Figure 15-8. 15.6 Programming Considerations When the MMIIC module detects an arbitration loss in master mode, it will release both SDA and SCL lines immediately. But if there are no further STOP conditions detected, the module will hang up. Therefore, it is recommended to have time-out software to recover from such ill condition. The software can start the time-out counter by looking at the MMBB (Bus Busy) flag in the MIMCR and reset the counter on the completion of one byte transmission. If a time-out occur, software can clear the MMEN bit (disable MMIIC module) to release the bus, and hence clearing the MMBB flag. This is the only way to clear the MMBB flag by software if the module hangs up due to a no STOP condition received. The MMIIC can resume operation again by setting the MMEN bit. Data Sheet 330 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Programming Considerations (a) Master Transmit Mode START Address 0 ACK TX Data1 ACK TX DataN ACK STOP MMTXBE=0 MMRW=0 MMAST=1 Data1 MMDTR MMTXBE=1 MMTXIF=1 Data2 MMDTR MMTXBE=1 MMTXIF=1 Data3 MMDTR MMTXBE=1 MMNAKIF=1 MMTXIF=1 MMAST=0 DataN+2 MMDTR MMTXBE=0 (b) Master Receive Mode START Address 1 ACK RX Data1 ACK RX DataN NAK STOP MMRXBF=0 MMRW=1 MMAST=1 MMTXBE=0 (dummy data MMDTR) Data1 MMDRR MMRXIF=1 MMRXBF=1 DataN MMDRR MMNAKIF=1 MMRXIF=1 MMAST=0 MMRXBF=1 (c) Slave Transmit Mode START Address 1 ACK TX Data1 ACK TX DataN NAK STOP MMTXBE=1 MMRXBF=0 MMRXIF=1 MMRXBF=1 MMATCH=1 MMSRW=1 Data1 MMDTR MMTXBE=1 MMTXIF=1 Data2 MMDTR MMTXBE=1 MMNAKIF=1 MMTXIF=1 MMTXBE=0 DataN+2 MMDTR (d) Slave Receive Mode START Address 0 ACK RX Data1 ACK RX DataN ACK STOP MMTXBE=0 MMRXBF=0 MMRXIF=1 MMRXBF=1 MMATCH=1 MMSRW=0 Data1 MMDRR MMRXIF=1 MMRXBF=1 DataN MMDRR MMRXIF=1 MMRXBF=1 Shaded data packets indicate transmissions by the MCU Figure 15-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Multi-Master IIC Interface (MMIIC) Data Sheet 331 Multi-Master IIC Interface (MMIIC) Data Sheet 332 Multi-Master IIC Interface (MMIIC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 16. Analog-to-Digital Converter (ADC) 16.1 Contents 16.2 16.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 16.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 16.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16.7.1 ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 16.7.2 ADC Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . 341 16.7.3 ADC Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . 341 16.7.4 ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . 341 16.7.5 ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . 341 16.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 16.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .342 16.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 16.8.3 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . 346 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 333 Analog-to-Digital Converter (ADC) 16.2 Introduction This section describes the analog-to-digital convert (ADC). The ADC is a 6-channel 10-bit linear successive approximation ADC. 16.3 Features Features of the ADC module include: * * * * * * * * Six channels with multiplexed input High impedance buffered input Linear successive approximation with monotonicity 10-Bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock Conversion result justification - 8-bit truncated mode - Right justified mode - Left justified mode - Left justified sign mode Data Sheet 334 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Functional Descriptions Addr. $003C Register Name Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: ADC Data Register High Write: (ADRH) Reset: Read: ADC Data Register Low (ADRL) Write: Reset: Read: ADC Clock Register (ADCLK) Write: Reset: Bit 7 COCO 0 ADx R 0 ADx R 0 ADIV2 0 6 AIEN 0 ADx R 0 ADx R 0 ADIV1 0 5 ADCO 0 ADx R 0 ADx R 0 ADIV0 0 4 ADCH4 1 ADx R 0 ADx R 0 ADICLK 0 3 ADCH3 1 ADx R 0 ADx R 0 MODE1 0 R 2 ADCH2 1 ADx R 0 ADx R 0 MODE0 1 = Reserved 1 ADCH1 1 ADx R 0 ADx R 0 0 0 Bit 0 ADCH0 1 ADx R 0 ADx R 0 0 R 0 $003D $003E $003F = Unimplemented Figure 16-1. ADC I/O Register Summary 16.4 Functional Descriptions The ADC provides six pins for sampling external sources at pins PTA4/ADC0-PTA7/ADC3 and PTB6/ADC4-PTB7/ADC5. An analog multiplexer allows the single ADC converter to select one of ten ADC channels as ADC voltage in (VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter. When the conversion is completed, ADC places the result in the ADC data register, high and low byte (ADRH and ADRL), and sets a flag or generates an interrupt. Figure 16-2 shows the structure of the ADC module. 16.4.1 ADC Port I/O Pins PTA4-PTA7 and PTB6-PTB7 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits, ADCH[4:0], define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 335 Analog-to-Digital Converter (ADC) logic and can be used as general-purpose I/O pins. Writes to the port data register or data direction register will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the pin condition if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read. INTERNAL DATA BUS READ DDRAx/DDRBx WRITE DDRAx/DDRBx RESET WRITE PTAx/PTBx DDRAx/DDRBx PTAx/PTBx PTAx/PTBx DISABLE READ PTAx/PTBx ADC0-ADC5 (6 CHANNELS) DISABLE ADC DATA REGISTERS ADRH ADRL VREFH VREFL 1.2V BANDGAP REFERENCE CHANNEL SELECT VLCD INTERRUPT LOGIC CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) AIEN COCO CGMXCLK BUS CLOCK ADC CLOCK ADCH[4:0] CLOCK GENERATOR ADIV[2:0] ADICLK Figure 16-2. ADC Block Diagram Data Sheet 336 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Functional Descriptions 16.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale). If the input voltage equals VREFL, the ADC converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. All other input voltages will result in $3FF if greater than VREFH and $000 if less than VREFL. NOTE: Input voltage should not exceed the analog supply voltages. 16.4.3 Conversion Time Conversion starts after a write to the ADSCR. A conversion is between 16 and 17 ADC clock cycles, therefore: Conversion time = 16 to17 ADC cycles ADC frequency Number of bus cycles = conversion time x bus frequency The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is either the bus clock or CGMXCLK and is selectable by the ADICLK bit located in the ADC clock control register. The divide ratio is selected by the ADIV[2:0] bits. For example, if a 4MHz CGMXCLK is selected as the ADC input clock source, with a divide-by-2 prescale, and the bus speed is set at 8MHz: Conversion time = 16 to 17 ADC cycles = 8 to 8.5 s 4MHz / 2 Number of bus cycles = 8s x 8MHz = 64 to 68 cycles NOTE: The ADC frequency must be between fADIC minimum and fADIC maximum to meet ADC specifications. See 24.12 5V ADC Electrical Characteristics and 24.13 3.3V ADC Electrical Characteristics. Since an ADC cycle may be comprised of several bus cycles (eight in the previous example) and the start of a conversion is initiated by a bus cycle write to the ADSCR, from zero to four additional bus cycles may occur before the start of the initial ADC cycle. This results in a fractional ADC cycle and is represented as the 17th cycle. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 337 Analog-to-Digital Converter (ADC) 16.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel, filling the ADC data register (ADRH:ADRL) with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after each conversion and can be cleared by writing to the ADC status and control register or reading of the ADRL data register. 16.4.5 Result Justification The conversion result may be formatted in four different ways. * * * * Left justified Right justified Left justified sign data mode 8-bit truncation All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock control register (ADCLK). Left justification will place the eight most significant bits (MSB) in the ADC data register high (ADRH). This may be useful if the result is to be treated as an 8-bit result where the least significant two bits, located in the ADC data register low (ADRL) can be ignored. However, ADRL must be read after ADRH or else the interlocking will prevent all new conversions from being stored. Right justification will place only the two MSBs in the corresponding ADC data register high (ADRH) and the eight LSB bits in ADC data register low (ADRL). This mode of operation typically is used when a 10-bit unsigned result is desired. Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Data Sheet 338 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Functional Descriptions Finally, 8-bit truncation mode will place the eight MSBs in ADC data register low (ADRL). The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. NOTE: Quantization error is affected when only the most significant eight bits are used as a result. See Figure 16-3. 8-BIT 10-BIT RESULT RESULT 003 00B 00A 009 002 008 007 006 005 001 004 003 002 001 000 000 1/2 1 1/2 1/2 2 1/2 3 1/2 4 1/2 5 1/2 1 1/2 6 1/2 7 1/2 8 1/2 9 1/2 2 1/2 INPUT VOLTAGE REPRESENTED AS 10-BIT INPUT VOLTAGE REPRESENTED AS 8-BIT WHEN TRUNCATION IS USED, ERROR FROM IDEAL 8-BIT = 3/8 LSB DUE TO NON-IDEAL QUANTIZATION. IDEAL 10-BIT CHARACTERISTIC WITH QUANTIZATION = 1/2 IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = 1/2 10-BIT TRUNCATED TO 8-BIT RESULT Figure 16-3. 8-Bit Truncation Mode Error 16.4.6 Monotonicity The conversion process is monotonic and has no missing codes. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 339 Analog-to-Digital Converter (ADC) 16.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The interrupt vector is defined in Table 2-1 . Vector Addresses. 16.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 16.6.1 Wait Mode The ADC continues normal operation in wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits to logic 1's before executing the WAIT instruction. 16.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 16.7 I/O Signals The ADC module has ten channels, six channels are shared with port A and port B I/O pins; two channels are the ADC voltage reference inputs, VREFH and VREFL; one channel is the VLCD input; and one channel is the 1.2V bandgap reference voltage. Data Sheet 340 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) I/O Signals 16.7.1 ADC Voltage In (VADIN) VADIN is the input voltage signal from one of the ten channels to the ADC module. 16.7.2 ADC Analog Power Pin (VDDA) The ADC analog portion uses VDDA as its power pin. Connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 16.7.3 ADC Analog Ground Pin (VSSA) The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. NOTE: On the 64-pin and 80-pin MC68HC908LJ24, VSSA is internally bonded to VSS. 16.7.4 ADC Voltage Reference High Pin (VREFH) VREFH is the power supply for setting the reference voltage VREFH. Connect the VREFH pin to the same voltage potential as VDDA. There will be a finite current associated with VREFH (see 24.12 5V ADC Electrical Characteristics). NOTE: Route VREFH carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 16.7.5 ADC Voltage Reference Low Pin (VREFL) VREFL is the lower reference supply for the ADC. Connect the VREFL pin to the same voltage potential as VSSA. There will be a finite current associated with VREFL(see 24.12 5V ADC Electrical Characteristics). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 341 Analog-to-Digital Converter (ADC) 16.8 I/O Registers These I/O registers control and monitor operation of the ADC: * * * ADC status and control register, (ADSCR) ADC data register (ADRH:ADRL) ADC clock control register (ADCLK) 16.8.1 ADC Status and Control Register This section describes the function of the ADC status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion. Address: Read: Write: Reset: 0 $003C COCO AIEN 0 ADCO 0 ADCH4 1 ADCH3 1 ADCH2 1 ADCH1 1 ADCH0 1 = Unimplemented Figure 16-4. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADSCR is written, or whenever the ADC clock control register is written, or whenever the ADC data register low, ADRL, is read. If the AIEN bit is logic 1, the COCO bit always read as logic 0, CPU to service the ADC interrupt will be generated at the end if an ADC conversion. Reset clears the COCO bit. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register, ADR0, is read or the ADSCR is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled Data Sheet 342 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) I/O Registers ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADC data register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels when not in auto-scan mode. The five channel select bits are detailed in Table 16-1. NOTE: Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. Recovery from the disabled state requires one conversion cycle to stabilize. Table 16-1. MUX Channel Select ADCH4 0 0 0 0 0 0 0 0 0 1 1 1 1 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 1 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 0 1 1 ADCH0 0 1 0 1 0 1 0 1 0 0 1 0 1 ADC Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC28 ADC29 ADC30 ADC powered-off Input Select PTA4 PTA5 PTA6 PTA7 PTB6 PTB7 1.2V Bandgap reference VLCD Reserved VREFH (see Note 2) VREFL (see Note 2) -- NOTES: 1. If any reserved channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 343 Analog-to-Digital Converter (ADC) 16.8.2 ADC Data Register The ADC data register consist of a pair of 8-bit registers: high byte (ADRH), and low byte (ADRL). This pair form a 16-bit register to store the 10-bit ADC result for the selected ADC result justification mode. In 8-bit truncated mode, the ADRL holds the eight most significant bits (MSBs) of the 10-bit result. The ADRL is updated each time an ADC conversion completes. In 8-bit truncated mode, ADRL contains no interlocking with ADRH. (See Figure 16-5 . ADRH and ADRL in 8-Bit Truncated Mode.) Addr. $003D Register Name Read: ADC Data Register High Write: (ADRH) Reset: Read: ADC Data Register Low Write: (ADRL) Reset: Bit 7 0 R 0 AD9 R 0 6 0 R 0 AD8 R 0 5 0 R 0 AD7 R 0 4 0 R 0 AD6 R 0 3 0 R 0 AD5 R 0 2 0 R 0 AD4 R 0 1 0 R 0 AD3 R 0 Bit 0 0 R 0 AD2 R 0 $003E Figure 16-5. ADRH and ADRL in 8-Bit Truncated Mode In right justified mode the ADRH holds the two MSBs, and the ADRL holds the eight least significant bits (LSBs), of the 10-bit result. ADRH and ADRL are updated each time a single channel ADC conversion completes. Reading ADRH latches the contents of ADRL. Until ADRL is read all subsequent ADC results will be lost. (See Figure 16-6 . ADRH and ADRL in Right Justified Mode.) Addr. $003D Register Name Read: ADC Data Register High Write: (ADRH) Reset: Read: ADC Data Register Low Write: (ADRL) Reset: Bit 7 0 R 0 AD7 R 0 6 0 R 0 AD6 R 0 5 0 R 0 AD5 R 0 4 0 R 0 AD4 R 0 3 0 R 0 AD3 R 0 2 0 R 0 AD2 R 0 1 AD9 R 0 AD1 R 0 Bit 0 AD8 R 0 AD0 R 0 $003E Figure 16-6. ADRH and ADRL in Right Justified Mode Data Sheet 344 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) I/O Registers In left justified mode the ADRH holds the eight most significant bits (MSBs), and the ADRL holds the two least significant bits (LSBs), of the 10-bit result. The ADRH and ADRL are updated each time a single channel ADC conversion completes. Reading ADRH latches the contents of ADRL. Until ADRL is read all subsequent ADC results will be lost. (See Figure 16-7 . ADRH and ADRL in Left Justified Mode.) Addr. $003D Register Name Read: ADC Data Register High Write: (ADRH) Reset: Read: ADC Data Register Low Write: (ADRL) Reset: Bit 7 AD9 R 0 AD1 R 0 6 AD8 R 0 AD0 R 0 5 AD7 R 0 0 R 0 4 AD6 R 0 0 R 0 3 AD5 R 0 0 R 0 2 AD4 R 0 0 R 0 1 AD3 R 0 0 R 0 Bit 0 AD2 R 0 0 R 0 $003E Figure 16-7. ADRH and ADRL in Left Justified Mode In left justified sign mode the ADRH holds the eight MSBs with the MSB complemented, and the ADRL holds the two least significant bits (LSBs), of the 10-bit result. The ADRH and ADRL are updated each time a single channel ADC conversion completes. Reading ADRH latches the contents of ADRL. Until ADRL is read all subsequent ADC results will be lost. (See Figure 16-8 . ADRH and ADRL in Left Justified Sign Data Mode.) Addr. $003D Register Name Read: ADC Data Register High Write: (ADRH) Reset: Read: ADC Data Register Low Write: (ADRL) Reset: Bit 7 AD9 R 0 AD1 R 0 6 AD8 R 0 AD0 R 0 5 AD7 R 0 0 R 0 4 AD6 R 0 0 R 0 3 AD5 R 0 0 R 0 2 AD4 R 0 0 R 0 1 AD3 R 0 0 R 0 Bit 0 AD2 R 0 0 R 0 $003E Figure 16-8. ADRH and ADRL in Left Justified Sign Data Mode MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 345 Analog-to-Digital Converter (ADC) 16.8.3 ADC Clock Control Register The ADC clock control register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F ADIV2 0 ADIV1 0 ADIV0 0 ADICLK 0 MODE1 0 R MODE0 1 = Reserved 0 0 R 0 0 = Unimplemented Figure 16-9. ADC Clock Control Register (ADCLK) ADIV[2:0] -- ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 16-2 shows the available clock configurations. The ADC clock should be set to between 32kHz and 2MHz. Table 16-2. ADC Clock Divide Ratio ADIV2 0 0 0 0 1 X = don't care ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC input clock / 1 ADC input clock / 2 ADC input clock / 4 ADC input clock / 8 ADC input clock / 16 ADICLK -- ADC Input Clock Select Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. Data Sheet 346 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) I/O Registers If the external clock (CGMXCLK) is equal to or greater than 1MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at fADIC, correct operation can be guaranteed. 1 = Internal bus clock 0 = External clock, CGMXCLK fADIC = CGMXCLK or bus frequency ADIV[2:0] MODE1 and MODE0 -- Modes of Result Justification MODE1 and MODE0 selects between four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode. Table 16-3. ADC Mode Select MODE1 0 0 1 1 MODE0 0 1 0 1 ADC Clock Rate 8-bit truncated mode Right justified mode Left justified mode Left justified sign data mode MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Analog-to-Digital Converter (ADC) Data Sheet 347 Analog-to-Digital Converter (ADC) Data Sheet 348 Analog-to-Digital Converter (ADC) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 17. Liquid Crystal Display (LCD) Driver 17.1 Contents 17.2 17.3 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Pin Name Conventions and I/O Register Addresses . . . . . . . 350 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 17.5.1 LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 17.5.2 LCD Voltages (VLCD, VLCD1, VLCD2, VLCD3) . . . . . . . . . . . 356 17.5.3 LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 17.5.4 Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . . 357 17.5.5 Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 17.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 17.7.1 BP0-BP3 (Backplane Drivers) . . . . . . . . . . . . . . . . . . . . . . 360 17.7.2 FP0-FP32 (Frontplane Drivers) . . . . . . . . . . . . . . . . . . . . . 362 17.8 Seven Segment Display Connection . . . . . . . . . . . . . . . . . . . 366 17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 17.9.1 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . 369 17.9.2 LCD Clock Register (LCDCLK) . . . . . . . . . . . . . . . . . . . . . 371 17.9.3 LCD Data Registers (LDAT1-LDAT17) . . . . . . . . . . . . . . . 373 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 349 Liquid Crystal Display (LCD) Driver 17.2 Introduction This section describes the liquid crystal display (LCD) driver module. The LCD driver module can drive a maximum of 33 frontplanes and 4 backplanes, depending on the LCD duty selected. 17.3 Features Features of the LCD driver module include the following: * Software programmable driver segment configurations: - 32 frontplanes x 4 backplanes (128 segments) - 33 frontplanes x 3 backplanes (99 segments) - 33 frontplanes x 1 backplane (33 segments) * * LCD bias voltages generated by internal resistor ladder Software programmable contrast control 17.4 Pin Name Conventions and I/O Register Addresses Three dedicated I/O pins are for the backplanes, BP0-BP2; sixteen dedicated I/O pins are for the frontplanes, FP1-FP10 and FP27-FP32; and the sixteen frontplanes, FP11-FP26, are shared with port C and E pins. FP0 and BP3 shares the same pin and configured by the DUTY[1:0] bits in the LCD clock register. The full names of the LCD output pins are shown in Table 17-1. The generic pin names appear in the text that follows. Table 17-1. Pin Name Conventions LCD Generic Pin Name FP0/BP3 BP0-BP2 FP1-FP10 FP11-FP18 FP19-FP26 FP27-FP32 Full MCU Pin Name FP0/BP3 BP0-BP2 FP1-FP10 PTE0/FP11-PTE7/FP18 PTC0/FP19-PTC7/FP26 FP27-FP32 Pin Selected for LCD Function by: -- -- -- PEE in CONFIG2 PCEL:PCEH in CONFIG2 -- Data Sheet 350 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Pin Name Conventions and I/O Register Addresses Addr. $004F Register Name Read: LCD Clock Register Write: (LCDCLK) Reset: Read: LCD Control Register Write: (LCDCR) Reset: Read: LCD Data Register 1 Write: (LDAT1) Reset: Read: LCD Data Register 2 Write: (LDAT2) Reset: Read: LCD Data Register 3 Write: (LDAT3) Reset: Read: LCD Data Register 4 Write: (LDAT4) Reset: Read: LCD Data Register 5 Write: (LDAT5) Reset: Read: LCD Data Register 6 Write: (LDAT6) Reset: Read: LCD Data Register 7 Write: (LDAT7) Reset: Read: LCD Data Register 8 Write: (LDAT8) Reset: Bit 7 0 0 LCDE 0 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U F13B3 U F15B3 U U = Unaffected 6 FCCTL1 0 0 0 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U F13B2 U F15B2 U 5 FCCTL0 0 FC 0 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U F13B1 U F15B1 U 4 DUTY1 0 LC 0 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U F13B0 U F15B0 U 3 DUTY0 0 LCCON3 0 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U F12B3 U F14B3 U 2 LCLK2 0 LCCON2 0 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U F12B2 U F14B2 U 1 LCLK1 0 LCCON1 0 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U F12B1 U F14B1 U Bit 0 LCLK0 0 LCCON0 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U F12B0 U F14B0 U $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 = Unimplemented Figure 17-1. LCD I/O Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 351 Liquid Crystal Display (LCD) Driver $005A Read: LCD Data Register 9 Write: (LDAT9) Reset: Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset: Read: LCD Data Register 14 Write: (LDAT14) Reset: Read: LCD Data Register 15 Write: (LDAT15) Reset: Read: LCD Data Register 16 Write: (LDAT16) Reset: Read: LCD Data Register 17 Write: (LDAT17) Reset: F17B3 U F19B3 U F21B3 U F23B3 U F25B3 U F27B3 U F29B3 U F31B3 U F17B2 U F19B2 U F21B2 U F23B2 U F25B2 U F27B2 U F29B2 U F31B2 U F17B1 U F19B1 U F21B1 U F23B1 U F25B1 U F27B1 U F29B1 U F31B1 U F17B0 U F19B0 U F21B0 U F23B0 U F25B0 U F27B0 U F29B0 U F31B0 U F16B3 U F18B3 U F20B3 U F22B3 U F24B3 U F26B3 U F28B3 U F30B3 U F32B3 U F16B2 U F18B2 U F20B2 U F22B2 U F24B2 U F26B2 U F28B2 U F30B2 U F32B2 U F16B1 U F18B1 U F20B1 U F22B1 U F24B1 U F26B1 U F28B1 U F30B1 U F32B1 U F16B0 U F18B0 U F20B0 U F22B0 U F24B0 U F26B0 U F28B0 U F30B0 U F32B0 U $005B $005C $005D $005E $005F $0060 $0061 $0062 U = Unaffected = Unimplemented Figure 17-1. LCD I/O Register Summary Data Sheet 352 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Functional Description 17.5 Functional Description Figure 17-2 shows a block diagram of the LCD driver module, and Figure 17-3 shows a simplified schematic of the LCD system. The LCD driver module uses a 1/3 biasing method. The LCD power is supplied by the VLCD pin. Voltages VLCD1, VLCD2, and VLCD3 are generated by an internal resistor ladder. The LCD data registers, LDAT1-LDAT17, control the LCD segments' ON/OFF, with each data register controlling two frontplanes. When a logic 1 is written to a FxBx bit in the data register, the corresponding frontplane-backplane segment will turn ON. When a logic 0 is written, the the segment will turn OFF. When the LCD driver module is disabled (LCDE = 0), the LCD display will be OFF, all backplane and frontplane drivers have the same potential as VDD. The resistor ladder is disconnected from VDD to reduce power consumption. PTE0/FP11 PTE1/FP12 PTE2/FP13 PTE3/FP14 PTE4/FP15 PTE5/FP16 PTE6/FP17 PTE7/FP18 FP10 FP5 FP6 FP7 FP8 FP9 PORT-E LOGIC PORT-C LOGIC LCD FRONTPLANE DRIVER AND DATA LATCH FP4 FP3 FP2 FP1 FP0/BP3 BP2 BP1 BP0 1/3 1/4 PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 PTC4/FP23 PTC5/FP24 PTC6/FP25 PTC7/FP26 FP27 FP28 FP29 FP30 FP31 FP32 LCDE (LCDC) DRIVER INTERNAL BUS STATE CONTROL 1/1 1/3 1/4 BACKPLANE Figure 17-2. LCD Block Diagram MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 353 Liquid Crystal Display (LCD) Driver LCD FP0 FP1 FP24 BP0 BP1 BP2 RFP VLCD VLCD RLCD RLCD RLCD VLCD1 VLCD2 VLCD3 Vbias VR BIAS CONTROL RFP RFP RBP RBP RBP LCCON[3:0] Figure 17-3. Simplified LCD Schematic (1/3 Duty, 1/3 Bias) Data Sheet 354 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Functional Description 17.5.1 LCD Duty The setting of the LCD output waveform duty is dependent on the number of backplane drivers required. Three LCD duties are available: * * * Static duty -- BP0 is used only 1/3 duty -- BP0, BP1, and BP3 are used 1/4 duty -- BP0, BP1, BP2, and BP3 are used When the LCD driver module is enabled the backplane waveforms for the selected duty are driven out of the backplane pins. The backplane waveforms are periodic and are shown are shown in Figure 17-5, Figure 17-6, and Figure 17-7. 17.5.2 LCD Voltages (VLCD, VLCD1, VLCD2, VLCD3) The voltage VLCD is from the VLCD pin and must not exceed VDD. VLCD1, VLCD2, and VLCD3 are internal bias voltages for the LCD driver waveforms. They are derived from VLCD using a resistor ladder (see Figure 17-3). The relative potential of the LCD voltages are: * * * * VLCD = VDD VLCD1 = 2/3 x (VLCD - Vbias) VLCD2 = 1/3 x (VLCD - Vbias) VLCD3 = Vbias The VLCD3 bias voltage, Vbias, is controlled by the LCD contrast control bits, LCCON[2:0]. 17.5.3 LCD Cycle Frame The LCD driver module uses the CGMXCLK (see Section 7. Oscillator (OSC))as the input reference clock. This clock is divided to produce the LCD waveform base clock, LCDCLK, by configuring the LCLK[2:0] bits in the LCD clock register. The LCDCLK clocks the backplane and the frontplane output waveforms. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 355 Liquid Crystal Display (LCD) Driver The LCD cycle frame is determined by the equation: 1 LCD WAVEFORM BASE CLOCK x DUTY LCD CYCLE FRAME = For example, for 1/3 duty and 256Hz waveform base clock: LCD CYCLE FRAME = 1 256 x (1/3) = 11.72 ms 17.5.4 Fast Charge and Low Current The default value for each of the bias resistors (see Figure 17-3), RLCD, in the resistor ladder is approximately 37k at VLCD = 3V. The relatively high current drain through the 37k resistor ladder may not be suitable for some LCD panel connections. Lowering this current is possible by setting the LC bit in the LCD control register, switching the RLCD value to 146k. Although the lower current drain is desirable, but in some LCD panel connections, the higher current is required to drive the capacitive load of the LCD panel. In most cases, the higher current is only required when the LCD waveforms change state (the rising and falling edges in the LCD output waveforms). The fast charge option is designed to have the high current for the switching and the low current for the steady state. Setting the FC bit in the LCD control register selects the fast charge option. The RLCD value is set to 37k (for high current) for a fraction of time for each LCD waveform switching edge, and then back to 146k for the steady state period. The duration of the fast charge time is set by configuring the FCCTL[1:0] bits in the LCD clock register, and can be LCDCLK/32, LCDCLK/64, or LCDCLK/128. Figure 17-4 shows the fast charge clock relative to the BP0 waveform. Data Sheet 356 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Low-Power Modes LCDCLK LCD WAVEFORM EXAMPLE: BP0 FAST CHARGE CLOCK HIGH CURRENT SELECTED BEFORE SWITCHING EDGE, PERIOD IS DEFINED BY FCCTL[1:0] Figure 17-4. Fast Charge Timing 17.5.5 Contrast Control The contrast of the connected LCD panel can be adjusted by configuring the LCCON[3:0] bits in the LCD control register. The LCCON[3:0] bits provide a 16-step contrast control, which adjusts the bias voltage in the resistor ladder for LCD voltage, VLCD3. The relative voltages, VLCD1 and VLCD2, are altered accordingly. For example, setting LCCON[3:0] = $F, the relative panel potential voltage (VLCD - VLCD3) is reduced from maximum 3.3V to approximate 2.45V. The VLCD voltage can be monitored by the ADC channel, ADC7, and then adjustments to the bias voltage by the user software to provide automatic contrast control. 17.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 357 Liquid Crystal Display (LCD) Driver 17.6.1 Wait Mode The LCD driver module continues normal operation in wait mode. If the LCD is not required in wait mode, power down the LCD module by clearing the LCDE bit before executing the WAIT instruction. 17.6.2 Stop Mode For continuous LCD module operation in stop mode, the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XCLKEN is set, CGMXCLK continues to drive the LCD module. If STOP_XCLKEN bit is cleared, the LCD module is inactive after the execution of a STOP instruction. The STOP instruction does not affect LCD register states. LCD module operation resumes after an external interrupt. To further reduce power consumption, the LCD module should be powered-down by clearing the LCDE bit before executing the STOP instruction. 17.7 I/O Signals The LCD driver module has thirty-six (36) output pins and shares eight of them with port C I/O pins and eight with port E I/O pins. * * * * * * FP0/BP3 (multiplexed; selected as FP0 or BP3 by DUTY[1:0]) BP0-BP2 FP1-FP10 FP11-FP18 (shared with port E) FP19-FP26 (shared with port C) FP27-FP32 Data Sheet 358 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Signals 17.7.1 BP0-BP3 (Backplane Drivers) BP0-BP3 are the backplane driver output pins. These are connected to the backplane of the LCD panel. Depending on the LCD duty selected, the voltage waveforms in Figure 17-5, Figure 17-6, and Figure 17-7 appear on the backplane pins. BP3 pin is only used when 1/4 duty is selected. The pin becomes FP0 for static and 1/3 duty operations. DUTY = STATIC 1FRAME VLCD VLCD1 VLCD2 VLCD3 NOTES: 1. BP1, BP2, and BP3 are not used. 2. At static duty, 1FRAME is equal to the cycle of LCD waveform base clock. BP0 Figure 17-5. Static LCD Backplane Driver Waveform DUTY = 1/3 1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 BP0 BP1 BP2 NOTES: 1. BP3 is not used. 2. At 1/3 duty, 1FRAME has three times the cycle of LCD waveform base clock. Figure 17-6. 1/3 Duty LCD Backplane Driver Waveforms MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 359 Liquid Crystal Display (LCD) Driver DUTY = 1/4 1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 BP0 BP1 BP2 BP3 Figure 17-7. 1/4 Duty LCD Backplane Driver Waveforms Data Sheet 360 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Signals 17.7.2 FP0-FP32 (Frontplane Drivers) FP0-FP32 are the frontplane driver output pins. These are connected to the frontplane of the LCD panel. Depending on LCD duty selected and the contents in the LCD data registers, the voltage waveforms in Figure 17-8, Figure 17-9, Figure 17-10 and Figure 17-11 appear on the frontplane pins. FP11-FP18 are shared with port E I/O pins. These pins are configured for standard I/O or LCD use by the PEE bit in CONFIG2 register. FP19-FP26 are shared with port C I/O pins. These pins are configured for standard I/O or LCD use by the PCEL and PCEH bits in CONFIG2 register. DUTY = STATIC DATA LATCH: 1 = ON, 0 = OFF FxB0 -- -- -- 0 1FRAME FPx OUTPUT VLCD VLCD1 VLCD2 VLCD3 FxB0 -- -- -- 1 VLCD VLCD1 VLCD2 VLCD3 Figure 17-8. Static LCD Frontplane Driver Waveforms MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 361 Liquid Crystal Display (LCD) Driver DUTY = 1/3 DATA LATCH: 1 = ON, 0 = OFF FxB2 -- 0 FxB1 0 FxB0 0 1FRAME VLCD VLCD1 VLCD2 VLCD3 FxB2 -- 0 FxB1 0 FxB0 1 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 FPx OUTPUT FxB2 -- 0 FxB1 1 FxB0 0 FxB2 -- 1 FxB1 0 FxB0 0 FxB2 -- 0 FxB1 1 FxB0 1 FxB2 -- 1 FxB1 1 FxB0 0 FxB2 -- 1 FxB1 0 FxB0 1 FxB2 -- 1 FxB1 1 FxB0 1 Figure 17-9. 1/3 Duty LCD Frontplane Driver Waveforms Data Sheet 362 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Signals DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF FxB3 0 FxB2 0 FxB1 0 FxB0 0 1FRAME FPx OUTPUT VLCD VLCD1 VLCD2 VLCD3 FxB3 0 FxB2 0 FxB1 0 FxB0 1 FxB3 0 FxB2 0 FxB1 1 FxB0 0 FxB3 0 FxB2 0 FxB1 1 FxB0 1 FxB3 0 FxB2 1 FxB1 0 FxB0 0 FxB3 0 FxB2 1 FxB1 0 FxB0 1 FxB3 0 FxB2 1 FxB1 1 FxB0 0 FxB3 0 FxB2 1 FxB1 1 FxB0 1 Figure 17-10. 1/4 Duty LCD Frontplane Driver Waveforms MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 363 Liquid Crystal Display (LCD) Driver DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF FxB3 1 FxB2 0 FxB1 0 FxB0 0 FPx OUTPUT VLCD VLCD1 VLCD2 VLCD3 FxB3 1 FxB2 0 FxB1 0 FxB0 1 1FRAME FxB3 1 FxB2 0 FxB1 1 FxB0 0 FxB3 1 FxB2 0 FxB1 1 FxB0 1 FxB3 1 FxB2 1 FxB1 0 FxB0 0 FxB3 1 FxB2 1 FxB1 0 FxB0 1 FxB3 1 FxB2 1 FxB1 1 FxB0 0 FxB3 1 FxB2 1 FxB1 1 FxB0 1 Figure 17-11. 1/4 Duty LCD Frontplane Driver Waveforms (continued) Data Sheet 364 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Seven Segment Display Connection 17.8 Seven Segment Display Connection The following shows an example for connecting a 7-segment LCD display to the LCD driver. The example uses 1/3 duty cycle, with pins BP0, BP1, BP2, FP0, FP1, and FP2 connected as shown in Figure 17-12. The output waveforms are shown in Figure 17-13. FP CONNECTION a f b f BP CONNECTION a b BP0 (a, b COMMONED) g g e d c e d c BP1 (c, f, g COMMONED) BP2 (d, e COMMONED) FP2 (b, c COMMONED) FP1 (a, d, g COMMONED) FP0 (e, f COMMONED) The segment assignments for each bit in the data registers are: F1B3 LDAT1 $0052 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0 -- d FP1 g a -- e FP0 f -- F3B3 LDAT2 $0053 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0 -- -- -- -- -- -- FP2 c b To display the character "4": LDAT1 = X010X01X, LDAT2 = XXXXXX11 a LDAT1 $0052 LDAT2 $0053 X X 0 X 1 X 0 X X X 0 X 1 1 X 1 f e g d b c X = don't care Figure 17-12. 7-Segment Display Example MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 365 Liquid Crystal Display (LCD) Driver DUTY = 1/3 1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 BP0 BP1 BP2 F0B2 -- 0 F0B1 1 F0B0 0 FP0 F1B2 -- 0 F1B1 1 F1B0 0 FP1 F2B2 -- 0 F2B1 1 F2B0 1 FP2 Figure 17-13. BP0-BP2 and FP0-FP2 Output Waveforms for 7-Segment Display Example Data Sheet 366 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Seven Segment Display Connection The voltage waveform across the "f" segment of the LCD (between BP1 and FP0) is illustrated in Figure 17-14. As shown in the waveform, the voltage peaks reach the LCD-ON voltage, VLCD, therefore, the segment will be ON. +VLCD +VLCD1 +VLCD2 BP1-FP0 0 -VLCD2 -VLCD1 -VLCD Figure 17-14. "f" Segment Voltage Waveform The voltage waveform across the "e" segment of the LCD (between BP2 and FP0) is illustrated in Figure 17-15. As shown in the waveform, the voltage peaks do not reach the LCD-ON voltage, VLCD, therefore, the segment will be OFF. +VLCD +VLCD1 +VLCD2 0 -VLCD2 -VLCD1 -VLCD BP2-FP0 Figure 17-15. "e" Segment Voltage Waveform MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 367 Liquid Crystal Display (LCD) Driver 17.9 I/O Registers Nineteen (19) registers control LCD driver module operation: * * * LCD control register (LCDCR) LCD clock register (LCDCLK) LCD data registers (LDAT1-LDAT17) 17.9.1 LCD Control Register (LCDCR) The LCD control register (LCDCR): * * * Address: Read: Write: Reset: Enables the LCD driver module Selects bias resistor value and fast-charge control Selects LCD contrast $0051 Bit 7 LCDE 0 6 0 0 5 FC 0 4 LC 0 3 LCCON3 0 2 LCCON2 0 1 LCCON1 0 Bit 0 LCCON0 0 = Unimplemented Figure 17-16. LCD Control Register (LCDCR) LCDE -- LCD Enable This read/write bit enables the LCD driver module; the backplane and frontplane drive LCD waveforms out of BPx and FPx pins. Reset clears the LCDE bit. 1 = LCD driver module enabled 0 = LCD driver module disabled FC -- Fast Charge LC -- Low Current These read/write bits are used to select the value of the resistors in resistor ladder for LCD voltages. Reset clears the FC and LC bits. Data Sheet 368 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Registers Table 17-2. Resistor Ladder Selection FC X 0 1 LC 0 1 1 Action Each resistor is approximately 37 k (default) Each resistor is approximately 146 k Fast charge mode LCCON[3:0] -- LCD Contrast Control These read/write bits select the bias voltage, Vbias. This voltage controls the contrast of the LCD. Maximum contrast is set when LCCON[3:0] =%0000; minimum contrast is set when LCCON[3:0] =%1111. Table 17-3. LCD Bias Voltage Control LCCON3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LCCON2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LCCON1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LCCON0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bias Voltage (% of VDD) 0.6 2.9 5.2 7.4 9.6 11.6 13.5 15.3 17.2 18.8 20.5 22.0 23.6 25.0 26.4 27.7 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 369 Liquid Crystal Display (LCD) Driver 17.9.2 LCD Clock Register (LCDCLK) The LCD clock register (LCDCLK): * * * Address: Read: Write: Reset: 0 Selects the fast charge duty cycle Selects LCD driver duty cycle Selects LCD waveform base clock $004F Bit 7 0 6 FCCTL1 0 5 FCCTL0 0 4 DUTY1 0 3 DUTY0 0 2 LCLK2 0 1 LCLK1 0 Bit 0 LCLK0 0 = Unimplemented Figure 17-17. LCD Clock Register (LCDCLK) FCCTL[1:0] -- Fast Charge Duty Cycle Select These read/write bits select the duty cycle of the fast charge duration. Reset clears these bits. (See 17.5.4 Fast Charge and Low Current) Table 17-4. Fast Charge Duty Cycle Selection FCCTL1:FCCTL0 00 01 10 11 Fast Charge Duty Cycle In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/32. In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/64. In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/128. Not used Data Sheet 370 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Registers DUTY[1:0] -- Duty Cycle Select These read/write bits select the duty cycle of the LCD driver output waveforms. The multiplexed FP0/BP3 pin is controlled by the duty cycle selected. Reset clears these bits. Table 17-5. LCD Duty Cycle Selection DUTY1:DUTY0 00 01 10 11 Description Static selected; FP0/BP3 pin function as FP0. 1/3 duty cycle selected; FP0/BP3 pin functions as FP0. 1/4 duty cycle selected; FP0/BP3 pin functions as BP3. Not used LCLK[2:0] -- LCD Waveform Base Clock Select These read/write bits selects the LCD waveform base clock. Reset clears these bits. Table 17-6. LCD Waveform Base Clock Selection LCD Waveform Base Clock Frequency LCDCLK (Hz) fXTAL = 32.768kHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 128 256 512 1024 16384 32768 65536 256 128 64 32 -- -- -- fXTAL = 4.9152MHz -- -- -- -- 300 150 75 LCD Frame Rate fXTAL(1) = 32.768kHz 1/3 duty 85.3 42.7 21.3 10.7 -- -- -- Reserved 1/4 duty 64 32 16 8 -- -- -- LCD Frame Rate fXTAL = 4.9152MHz 1/3 duty -- -- -- -- 100 50 25 1/4 duty -- -- -- -- 75 37.5 18.75 LCLK2 LCLK1 LCLK0 Divide Ratio Notes: 1. fXTAL is the same as CGMXCLK (see Section 7. Oscillator (OSC)). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 371 Liquid Crystal Display (LCD) Driver 17.9.3 LCD Data Registers (LDAT1-LDAT17) The seventeen (17) LCD data registers enable and disable the drive to the corresponding LCD segments. Addr. $0052 Register Name Read: LCD Data Register 1 Write: (LDAT1) Reset: Read: LCD Data Register 2 Write: (LDAT2) Reset: Read: LCD Data Register 3 Write: (LDAT3) Reset: Read: LCD Data Register 4 Write: (LDAT4) Reset: Read: LCD Data Register 5 Write: (LDAT5) Reset: Read: LCD Data Register 6 Write: (LDAT6) Reset: Read: LCD Data Register 7 Write: (LDAT7) Reset: Read: LCD Data Register 8 Write: (LDAT8) Reset: Read: LCD Data Register 9 Write: (LDAT9) Reset: Bit 7 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U F13B3 U F15B3 U F17B3 U U = Unaffected 6 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U F13B2 U F15B2 U F17B2 U 5 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U F13B1 U F15B1 U F17B1 U 4 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U F13B0 U F15B0 U F17B0 U 3 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U F12B3 U F14B3 U F16B3 U 2 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U F12B2 U F14B2 U F16B2 U 1 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U F12B1 U F14B1 U F16B1 U Bit 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U F12B0 U F14B0 U F16B0 U $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A = Unimplemented Figure 17-18. LCD Data Registers 1-17 (LDAT1-LDAT17) Data Sheet 372 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver I/O Registers $005B Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset: Read: LCD Data Register 14 Write: (LDAT14) Reset: Read: LCD Data Register 15 Write: (LDAT15) Reset: Read: LCD Data Register 16 Write: (LDAT16) Reset: Read: LCD Data Register 17 Write: (LDAT17) Reset: F19B3 U F21B3 U F23B3 U F25B3 U F27B3 U F29B3 U F31B3 U F19B2 U F21B2 U F23B2 U F25B2 U F27B2 U F29B2 U F31B2 U F19B1 U F21B1 U F23B1 U F25B1 U F27B1 U F29B1 U F31B1 U F19B0 U F21B0 U F23B0 U F25B0 U F27B0 U F29B0 U F31B0 U F18B3 U F20B3 U F22B3 U F24B3 U F26B3 U F28B3 U F30B3 U F32B3 U F18B2 U F20B2 U F22B2 U F24B2 U F26B2 U F28B2 U F30B2 U F32B2 U F18B1 U F20B1 U F22B1 U F24B1 U F26B1 U F28B1 U F30B1 U F32B1 U F18B0 U F20B0 U F22B0 U F24B0 U F26B0 U F28B0 U F30B0 U F32B0 U $005C $005D $005E $005F $0060 $0061 $0062 U = Unaffected = Unimplemented Figure 17-18. LCD Data Registers 1-17 (LDAT1-LDAT17) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Liquid Crystal Display (LCD) Driver Data Sheet 373 Liquid Crystal Display (LCD) Driver Data Sheet 374 Liquid Crystal Display (LCD) Driver MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 18. Input/Output (I/O) Ports 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 380 18.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 381 18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 18.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 383 18.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 385 18.4.3 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . . 386 18.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 18.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . 387 18.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . 388 18.5.3 Port C LED Control Register (LEDC) . . . . . . . . . . . . . . . . . 389 18.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 18.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 390 18.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 392 18.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 18.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 394 18.7.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 395 18.7.3 Port E LED Control Register (LEDE) . . . . . . . . . . . . . . . . . 396 18.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 397 18.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . 398 18.8.3 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . . 399 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 375 Input/Output (I/O) Ports 18.2 Introduction Forty-eight (48) bidirectional input-output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0 Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Unaffected by reset PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 $0002 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Unaffected by reset DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0 Read: DDRB7 Data Direction Register B $0005 Write: (DDRB) Reset: 0 Read: DDRC7 Data Direction Register C Write: $0006 (DDRC) Reset: 0 Read: DDRD7 Data Direction Register D $0007 Write: (DDRD) Reset: 0 Figure 18-1. I/O Port Register Summary Data Sheet 376 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Introduction Addr. $0008 Register Name Read: Port E Data Register Write: (PTE) Reset: Bit 7 PTE7 U 6 PTE6 U DDRE6 0 PTF6 U DDRF6 0 0 0 LEDC6 0 LEDE6 0 LEDF6 0 5 PTE5 U DDRE5 0 PTF5 U DDRF5 0 LEDB5 0 LEDC5 0 LEDE5 0 LEDF5 0 4 PTE4 U DDRE4 0 PTF4 U DDRF4 0 LEDB4 0 LEDC4 0 LEDE4 0 LEDF4 0 3 PTE3 U DDRE3 0 PTF3 U DDRF3 0 LEDB3 0 LEDC3 0 LEDE3 0 LEDF3 0 2 PTE2 U DDRE2 0 PTF2 U DDRF2 0 LEDB2 0 LEDC2 0 LEDE2 0 LEDF2 0 1 PTE1 U DDRE1 0 PTF1 U DDRF1 0 LEDB1 0 LEDC1 0 LEDE1 0 LEDF1 0 Bit 0 PTE0 U DDRE0 0 PTF0 U DDRF0 0 LEDB0 0 LEDC0 0 LEDE0 0 LEDF0 0 Read: DDRE7 Data Direction Register E $0009 Write: (DDRE) Reset: 0 $000A Read: Port F Data Register Write: (PTF) Reset: PTF7 U Read: DDRF7 Data Direction Register F $000B Write: (DDRF) Reset: 0 $000C Read: Port-B LED Control Register Write: (LEDB) Reset: Read: Port-C LED Control Register Write: (LEDC) Reset: Read: Port-E LED Control Register Write: (LEDE) Reset: Read: Port-F LED Control Register Write: (LEDF) Reset: 0 0 LEDC7 0 LEDE7 0 LEDF7 0 $000D $000E $000F Figure 18-1. I/O Port Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 377 Input/Output (I/O) Ports Table 18-1. Port Control Register Bits Summary (Sheet 1 of 2) Port Bit 0 1 2 A 3 4 5 6 7 0 1 2 B 3 4 5 6 7 0 1 2 C 3 4 5 6 7 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRC7 LCD CONFIG2 ($001D) PCEH PCEL SCI TIM1 TIM2 ADC SCC1 ($0013) T1SC0 ($0025) T1SC1 ($0028) T2SC0 ($0030) T2SC1 ($0033) ADSCR ($003C) ENSCI ELS0B:ELS0A ELS1B:ELS1A ELS0B:ELS0A ELS1B:ELS1A ADCH[4:0] ADC ADSCR ($003C) ADCH[4:0] KBI KBIER ($001C) Module Control Module Register Control Bit KBIE0 KBIE1 KBIE2 KBIE3 Pin PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/ADC0 PTA5/ADC1 PTA6/ADC2 PTA7/ADC3 PTB0/TxD PTB1/RxD PTB2/T1CH0 PTB3/T1CH1 PTB4/T2CH0 PTB5/T2CH1 PTB6/ADC4 PTB7/ADC5 PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 PTC4/FP23 PTC5/FP24 PTC6/FP25 PTC7/FP26 Data Sheet 378 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Introduction Table 18-1. Port Control Register Bits Summary (Sheet 2 of 2) Port Bit 0 1 2 3 D (1) 4 5 6 7 0 1 2 E 3 4 5 6 7 0 1 2 F 3 4 5 6 7 DDR DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 KBI TIM DDRD5 DDRD6 KBI MMIIC DDRD7 DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 DDRE5 DDRE6 DDRE7 DDRF0 DDRF1 DDRF2 DDRF3 DDRF4 DDRF5 DDRF6 DDRF7 -- -- -- LCD CONFIG2 ($001D) PEE SPI RTC Module Control Module Register SPCR ($0010) RTCCOMR ($0040) SPCR ($0010) SPCR ($0010) RTCCOMR ($0040) KBIER ($001C) T1SC ($0020) KBIER ($001C) T2SC ($002B) KBIER ($001C) MMCR ($006C) KBIER ($001C) MMCR ($006C) Control Bit SPE CAL SPE SPE CAL KBIE4 PS[2:0] KBIE5 PS[2:0] KBIE6 MMEN KBIE7 MMEN Pin PTD0/SS/CALIN PTD1/MISO PTD2/MOSI PTD3/SPSCK/CALOUT PTD4/KBI4/T1CLK PTD5/KBI5/T2CLK PTD6/KBI6/SCL PTD7/KBI7/SDA PTE0/FP11 PTE1/FP12 PTE2/FP13 PTE3/FP14 PTE4/FP15 PTE5/FP16 PTE6/FP17 PTE7/FP18 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 Notes: 1. In addition to the standard I/O function on PTD0 and PTD3-PTD7 pins, these pins are shared with two other modules. For each of the pins, ONLY enable ONE module at any one time to avoid pin contention. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 379 Input/Output (I/O) Ports 18.3 Port A Port A is an 8-bit special function port that shares four of its port pins with the analog-to-digital converter (ADC) module and four of its port pins with the keyboard interrupt module (KBI). 18.3.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins. Address: $0000 Bit 7 Read: Write: Reset: Alternative Function: ADC3 ADC2 ADC1 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0 Unaffected by Reset ADC0 KBI3 KBI2 KBI1 KBI0 Figure 18-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[3:0] -- Keyboard Interrupt Channels 3 to 0 KBI[3:0] are pins used for the keyboard interrupt input. The corresponding input, KBI[3:0], can be enabled in the keyboard interrupt enable register, KBIER. Port pins used as KBI input will override any control from the port I/O logic. See Section 20. Keyboard Interrupt Module (KBI). Data Sheet 380 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port A ADC[3:0] -- ADC channels 0 to 3 ADC[3:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Section 16. Analog-to-Digital Converter (ADC). NOTE: Care must be taken when reading port A while applying analog voltages to ADC[3:0] pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTAx/ADCx pin, while PTA is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports. 18.3.2 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: $0004 Bit 7 Read: Write: Reset: DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0 Figure 18-3. Data Direction Register A (DDRA) DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 18-4 shows the port A I/O logic. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 381 Input/Output (I/O) Ports READ DDRA ($0004) WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) DDRAx PTAx PTAx READ PTA ($0000) Figure 18-4. Port A I/O Circuit When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-2 summarizes the operation of the port A pins. Table 18-2. Port A Pin Functions DDRA Bit Accesses to DDRA PTA Bit I/O Pin Mode Read/Write Read Write Accesses to PTA 0 1 X(1) X Input, Hi-Z(2) Output DDRA[7:0] DDRA[7:0] Pin PTA[7:0] PTA[7:0](3) PTA[7:0] Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. Data Sheet 382 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port B 18.4 Port B Port B is a 8-bit special function port that shares two of its port pins with the infrared serial communication interface (IRSCI) module, two of its port pins with the timer interface module 1 (TIM1) module, two of its port pins with the timer interface module 2 (TIM2), and two of its port pins with the ADC module. Port pins PTB0-PTB5 can be configured for direct LED drive. 18.4.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins. Address: $0001 Bit 7 Read: Write: Reset: Alternative Function: Additional Function: ADC5 ADC4 T2CH1 PTB7 6 PTB6 5 PTB5 4 PTB4 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0 Unaffected by reset T2CH0 T1CH1 T1CH0 RxD TxD LED drive LED drive LED drive LED drive LED drive LED drive Figure 18-5. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. TxD, RxD -- SCI Data I/O Pins The TxD and RxD pins are the transmit data output and receive data input for the IRSCI module. The enable SCI bit, ENSCI, in the SCI control register 1 enables the PTB0/TxD and PTB1/RxD pins as SCI TxD and RxD pins and overrides any control from the port I/O. See Section 13. Infrared Serial Communications Interface Module (IRSCI). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 383 Input/Output (I/O) Ports T1CH[1:0] -- Timer 1 Channel I/O Bits The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB2/T1CH0 and PTB3/T1CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Section 11. Timer Interface Module (TIM). T2CH[1:0] -- Timer 2 Channel I/O Bits The T2CH1 and T2CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB4/T2CH0 and PTB5/T2CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Section 11. Timer Interface Module (TIM). ADC[5:4] -- ADC Channels 5 and 4 ADC[5:4] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Section 16. Analog-to-Digital Converter (ADC). NOTE: Care must be taken when reading port B while applying analog voltages to ADC[5:4] pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTBx/ADCx pin, while PTB is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports. LED Drive -- Direct LED Drive Pins PTB0-PTB5 pins can be configured for direct LED drive. See 18.4.3 Port B LED Control Register (LEDB). Data Sheet 384 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port B 18.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: $0005 Bit 7 Read: Write: Reset: DDRB7 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0 Figure 18-6. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 18-7 shows the port B I/O logic. READ DDRB ($0005) WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) DDRBx PTBx PTBx READ PTB ($0001) Figure 18-7. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 385 Input/Output (I/O) Ports Table 18-3 summarizes the operation of the port B pins. Table 18-3. Port B Pin Functions DDRB Bit Accesses to DDRB PTB Bit I/O Pin Mode Read/Write Read Write Accesses to PTB 0 1 X(1) X Input, Hi-Z(2) Output DDRB[7:0] DDRB[7:0] Pin PTB[7:0] PTB[7:0](3) PTB[7:0] Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 18.4.3 Port B LED Control Register (LEDB) The port-B LED control register (LEDB) controls the direct LED drive capability on PTB5-PTB0 pins. Each bit is individually configurable and requires that the data direction register, DDRB, bit be configured as an output. When the IRSCI is enabled, setting the LEDB0 bit also enables high current (15mA) sink capability for the TxD pin. Address: $000C Bit 7 Read: Write: Reset: 0 0 0 6 0 5 LEDB5 0 4 LEDB4 0 3 LEDB3 0 2 LEDB2 0 1 LEDB1 0 Bit 0 LEDB0 0 Figure 18-8. Port B LED Control Register (LEDB) LEDB[5:0] -- Port B LED Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port B pin is configured for direct LED drive, with 15mA current sinking capability 0 = Corresponding port B pin is configured for standard drive Data Sheet 386 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port C 18.5 Port C Port C is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module. Port pins PTC0-PTC7 can be configured for direct LED drive. 18.5.1 Port C Data Register (PTC) The port C data register contains a data latch for each of the eight port C pins. Address: $0002 Bit 7 Read: Write: Reset: Alternative Function: FP26 FP25 FP24 PTC7 6 PTC6 5 PTC5 4 PTC4 3 PTC3 2 PTC2 1 PTC1 Bit 0 PTC0 Unaffected by reset FP23 FP22 FP21 FP20 FP19 Additional Function: LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive Figure 18-9. Port C Data Register (PTC) PTC[7:0] -- Port C Data Bits These read/write bits are software programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. FP[26:19] -- LCD Driver Frontplanes 26-19 FP[26:19] are pins used for the frontplane output of the LCD driver module. The enable bits, PCEH and PCEL, in the CONFIG2 register, determine whether the PTC7/FP26-PTC4/FP23 and PTC3/FP22-PTC0/FP19 pins are LCD frontplane driver pins or general-purpose I/O pins. See Section 17. Liquid Crystal Display (LCD) Driver. LED drive -- Direct LED Drive Pins PTC0-PTC7 pins can be configured for direct LED drive. See 18.5.3 Port C LED Control Register (LEDC). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 387 Input/Output (I/O) Ports 18.5.2 Data Direction Register C (DDRC) Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: $0006 Bit 7 Read: Write: Reset: DDRC7 0 6 DDRC6 0 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0 Figure 18-10. Data Direction Register C (DDRC) DDRC[7:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE: Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 18-11 shows the port C I/O logic. READ DDRC ($0006) WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) DDRCx PTCx PTCx READ PTC ($0002) Figure 18-11. Port C I/O Circuit Data Sheet 388 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port C When DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-4 summarizes the operation of the port C pins. Table 18-4. Port C Pin Functions DDRC Bit Accesses to DDRC PTC Bit I/O Pin Mode Read/Write Read Write Accesses to PTC 0 1 X(1) X Input, Hi-Z(2) Output DDRC[7:0] DDRC[7:0] Pin PTC[7:0] PTC[7:0](3) PTC[7:0] Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 18.5.3 Port C LED Control Register (LEDC) Port-C LED control register (LEDC) controls the direct LED drive capability on PTC7-PTC0 pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an output. Address: $000D Bit 7 Read: Write: Reset: LEDC7 0 6 LEDC6 0 5 LEDC5 0 4 LEDC4 0 3 LEDC3 0 2 LEDC2 0 1 LEDC1 0 Bit 0 LEDC0 0 Figure 18-12. Port C LED Control Register (LEDC) LEDC[7:0] -- Port C LED Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port C pin is configured for direct LED drive, with 15mA current sinking capability 0 = Corresponding port C pin is configured for standard drive MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 389 Input/Output (I/O) Ports 18.6 Port D Port D is an 8-bit special function port that shares its pins with the serial peripheral interface (SPI) module, keyboard interrupt module, RTC module, MMIIC module, and timer modules. 18.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: $0003 Bit 7 Read: Write: Reset: Alternative Function: KBI7/ SDA* KBI6/ SCL* KBI5/ T2CLK* PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0 Unaffected by reset KBI4/ T1CLK* SPSCK/ CALOUT* MOSI MISO SS/ CALIN* * These port pins are shared with two other modules. For each of the pins, ONLY enable ONE module at any one time to avoid pin contention. Figure 18-13. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. KBI[7:4] -- Keyboard Interrupt Channels 7 to 4 KBI[7:4] are pins used for the keyboard interrupt input. The corresponding input, KBI[7:4], can be enabled in the keyboard interrupt enable register, KBIER. Port pins used as KBI input will override any control from the port I/O logic. See Section 20. Keyboard Interrupt Module (KBI). Data Sheet 390 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port D SDA, SCL -- Multi-Master IIC Data and Clock Pins The SDA and SCL pins are multi-master IIC data and clock opendrain pins, enabled by setting the MMEN bit in the MMIIC control register (MMCR). Port pins used as MMIIC will override any control from the port I/O logic. See Section 15. Multi-Master IIC Interface (MMIIC). T2CLK -- TIM2 Clock Input Pin The T2CLK pin is the external clock input for TIM2, enabled by setting the prescaler select bits, PS[2:0] to %111, in the TIM2 status and control register (T2SC). Port pin used as T2CLK will override any control from the port I/O logic. See Section 11. Timer Interface Module (TIM). T1CLK -- TIM1 Clock Input Pin The T1CLK pin is the external clock input for TIM1, enabled by setting the prescaler select bits, PS[2:0] to %111, in the TIM1 status and control register (T1SC). Port pin used as T1CLK will override any control from the port I/O logic. See Section 11. Timer Interface Module (TIM). SPSCK, MOSI, MISO, and SS -- SPI Functional Pins These four pins are the SPI clock, master-output-slave-input, masterinput-slave-output, and slave select pins; enabled by setting the SPI enable bit, SPE, in the SPI control register (SPCR). Port pins used as SPI will override any control from the port I/O logic. See Section 14. Serial Peripheral Interface Module (SPI). CALOUT, CALIN -- RTC Calibration Pins The CALOUT and CALIN pins are RTC calibration pins, enabled by setting the CAL bit in the RTC calibration register (RTCCOMR). Port pins used for RTC calibration will override any control from the port I/O logic. See Section 12. Real Time Clock (RTC). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 391 Input/Output (I/O) Ports 18.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Bit 7 Read: Write: Reset: DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0 Figure 18-14. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 18-15 shows the port D I/O logic. READ DDRD ($0007) WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) DDRDx PTDx PTDx READ PTD ($0003) Figure 18-15. Port D I/O Circuit Data Sheet 392 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port D When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-5 summarizes the operation of the port D pins. Table 18-5. Port D Pin Functions DDRD Bit Accesses to DDRD PTD Bit I/O Pin Mode Read/Write Read Write Accesses to PTD 0 1 X(1) X Input, Hi-Z(2) Output DDRD[7:0] DDRD[7:0] Pin PTD[7:0] PTD[7:0](3) PTD[7:0] Notes: 1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 393 Input/Output (I/O) Ports 18.7 Port E Port E is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module. Port pins PTE0-PTE7 can be configured for direct LED drive. 18.7.1 Port E Data Register (PTE) The port E data register contains a data latch for each of the eight port E pins. Address: $0008 Bit 7 Read: Write: Reset: Alternative Function: FP18 FP17 FP16 PTE7 6 PTE6 5 PTE5 4 PTE4 3 PTE3 2 PTE2 1 PTE1 Bit 0 PTE0 Unaffected by reset FP15 FP14 FP13 FP12 FP11 Additional Function: LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive Figure 18-16. Port E Data Register (PTE) PTE[7:0] -- Port E Data Bits These read/write bits are software programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port E data. FP[18:11] -- LCD Driver Frontplanes 18-11 FP[18:11] are pins used for the frontplane output of the LCD driver module. The enable bit, PEE, in the CONFIG2 register, determines whether the PTE7/FP18-PTE0/FP11 pins are LCD frontplane driver pins or general-purpose I/O pins. See Section 17. Liquid Crystal Display (LCD) Driver. LED drive -- Direct LED Drive Pins PTE0-PTE7 pins can be configured for direct LED drive. See 18.7.3 Port E LED Control Register (LEDE). Data Sheet 394 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port E 18.7.2 Data Direction Register E (DDRE) Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: $0009 Bit 7 Read: Write: Reset: DDRE7 0 6 DDRE6 0 5 DDRE5 0 4 DDRE4 0 3 DDRE3 0 2 DDRE2 0 1 DDRE1 0 Bit 0 DDRE0 0 Figure 18-17. Data Direction Register E (DDRE) DDRE[7:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE: Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 18-18 shows the port E I/O logic. READ DDRE ($0009) WRITE DDRE ($0009) INTERNAL DATA BUS RESET WRITE PTE ($0008) DDREx PTEx PTEx READ PTE ($0008) Figure 18-18. Port E I/O Circuit MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 395 Input/Output (I/O) Ports When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-6 summarizes the operation of the port E pins. Table 18-6. Port E Pin Functions DDRE Bit Accesses to DDRE PTE Bit I/O Pin Mode Read/Write Read Write Accesses to PTE 0 1 X(1) X Input, Hi-Z(2) Output DDRE[7:0] DDRE[7:0] Pin PTE[7:0] PTE[7:0](3) PTE[7:0] Notes: 1. X = don't care; except. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 18.7.3 Port E LED Control Register (LEDE) The port-E LED control register (LEDE) controls the direct LED drive capability on PTE7-PTE0 pins. Each bit is individually configurable and requires that the data direction register, DDRE, bit be configured as an output. Address: $000E Bit 7 Read: Write: Reset: LEDE7 0 6 LEDE6 0 5 LEDE5 0 4 LEDE4 0 3 LEDE3 0 2 LEDE2 0 1 LEDE1 0 Bit 0 LEDE0 0 Figure 18-19. Port E LED Control Register (LEDE) LEDE[7:0] -- Port E LED Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port E pin is configured for direct LED drive, with 15mA current sinking capability 0 = Corresponding port E pin is configured for standard drive Data Sheet 396 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port F 18.8 Port F Port F is an 8-bit general-purpose I/O port. Port pins PTF0-PTF7 can be configured for direct LED drive. NOTE: PTF0-PTF7 are not available in the 64-pin packages. 18.8.1 Port F Data Register (PTF) The port F data register contains a data latch for each of the eight port F pins. Address: $000A Bit 7 Read: Write: Reset: PTF7 6 PTF6 5 PTF5 4 PTF4 3 PTF3 2 PTF2 1 PTF1 Bit 0 PTF0 Unaffected by Reset Additional Function: LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive Figure 18-20. Port F Data Register (PTF) PTF[7:0] -- Port F Data Bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on port F data. LED drive -- Direct LED Drive Pins PTF0-PTF7 pins can be configured for direct LED drive. See 18.8.3 Port F LED Control Register (LEDF). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 397 Input/Output (I/O) Ports 18.8.2 Data Direction Register F (DDRF) Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer. NOTE: For those devices packaged in a 64-pin package, PTF0-PTF7 are connected to ground internally. DDRF0-DDRF7 should be set to a 0 to configure PTF0-PTF7 as inputs. Address: $000B Bit 7 Read: Write: Reset: DDRF7 0 6 DDRF6 0 5 DDRF5 0 4 DDRF4 0 3 DDRF3 0 2 DDRF2 0 1 DDRF1 0 Bit 0 DDRF0 0 Figure 18-21. Data Direction Register F (DDRF) DDRF[7:0] -- Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[7:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input NOTE: Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 18-22 shows the port F I/O logic. READ DDRF ($000B) WRITE DDRF ($000B) INTERNAL DATA BUS RESET WRITE PTF ($000A) DDRFx PTFx PTFx READ PTF ($000A) Figure 18-22. Port F I/O Circuit Data Sheet 398 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Port F When DDRFx is a logic 1, reading address $000A reads the PTFx data latch. When DDRFx is a logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 18-7 summarizes the operation of the port F pins. Table 18-7. Port F Pin Functions DDRF Bit Accesses to DDRF PTF Bit I/O Pin Mode Read/Write Read Write Accesses to PTF 0 1 X(1) X Input, Hi-Z(2) Output DDRF[7:0] DDRF[7:0] Pin PTF[7:0] PTF[7:0](3) PTF[7:0] Notes: 1. X = don't care; except. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. 18.8.3 Port F LED Control Register (LEDF) Port-F LED control register (LEDF) controls the direct LED drive capability on PTF7-PTF0 pins. Each bit is individually configurable and requires that the data direction register, DDRF, bit be configured as an output. Address: $000F Bit 7 Read: Write: Reset: LEDF7 0 6 LEDF6 0 5 LEDF5 0 4 LEDF4 0 3 LEDF3 0 2 LEDF2 0 1 LEDF1 0 Bit 0 LEDF0 0 Figure 18-23. Port F LED Control Register (LEDF) LEDF[7:0] -- Port F LED Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port F pin is configured for direct LED drive, with 15mA current sinking capability 0 = Corresponding port F pin is configured for standard drive MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Input/Output (I/O) Ports Data Sheet 399 Input/Output (I/O) Ports Data Sheet 400 Input/Output (I/O) Ports MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 19. External Interrupt (IRQ) 19.1 Contents 19.2 19.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 19.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 19.5 19.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 405 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 405 19.2 Introduction The external interrupt (IRQ) module provides a maskable interrupt input. 19.3 Features Features of the IRQ module include the following: * * * * * * A dedicated external interrupt pin (IRQ) IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Internal pullup resistor MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor External Interrupt (IRQ) Data Sheet 401 External Interrupt (IRQ) 19.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 19-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears the interrupt latch. * The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic 1 The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. Data Sheet 402 External Interrupt (IRQ) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor External Interrupt (IRQ) Functional Description RESET ACK INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE IRQ VDD D CLR Q IRQF SYNCHRONIZER IRQ INTERRUPT REQUEST TO CPU FOR BIL/BIH INSTRUCTIONS CK IMASK MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 19-1. IRQ Module Block Diagram Addr. Register Name IRQ Status and Control Register (INTSCR) Read: Write: Reset: Bit 7 0 6 0 5 0 4 0 3 IRQF 2 0 ACK 1 IMASK 0 Bit 0 MODE 0 $001E 0 0 0 0 0 0 = Unimplemented Figure 19-2. IRQ I/O Port Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor External Interrupt (IRQ) Data Sheet 403 External Interrupt (IRQ) 19.4.1 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic 1 -- As long as the IRQ pin is at logic 0, IRQ remains active. * The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH of BIL instruction to read the logic level on the IRQ pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. MC68HC908LJ24/LK24 -- Rev. 2.1 External Interrupt (IRQ) Freescale Semiconductor Data Sheet 404 External Interrupt (IRQ) IRQ Module During Break Interrupts 19.5 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 23. Break Module (BRK).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. 19.6 IRQ Status and Control Register (INTSCR) The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: * * * * Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ and interrupt request Controls triggering sensitivity of the IRQ interrupt pin MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor External Interrupt (IRQ) Data Sheet 405 External Interrupt (IRQ) Address: $001E Bit 7 6 0 5 0 4 0 3 IRQF 2 0 ACK 0 0 0 0 0 0 1 IMASK 0 Bit 0 MODE 0 Read: Write: Reset: 0 = Unimplemented Figure 19-3. IRQ Status and Control Register (INTSCR) IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only Data Sheet 406 External Interrupt (IRQ) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 20. Keyboard Interrupt Module (KBI) 20.1 Contents 20.2 20.3 20.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 20.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 20.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 412 20.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 412 20.6.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 413 20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 20.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 414 20.2 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA3 and PTD4-PTD7. When a port pin is enabled for keyboard interrupt function (except PTD6 and PTD7), an internal 30k pullup device is also enabled on the pin. NOTE: PTD6/KBI6/SCL-PTD7/KBI7/SDA pins do not have internal pullup devices. These two pins are open-drain when configured as outputs. User should connect pullup devices when using these two pins for KBI function. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Data Sheet 407 Keyboard Interrupt Module (KBI) 20.3 Features Features of the keyboard interrupt module include the following: * * * * Addr. Register Name Read: Keyboard Status and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset: Eight keyboard interrupt pins with pullup devices Separate keyboard interrupt enable bits and one keyboard interrupt mask Programmable edge-only or edge- and level- interrupt sensitivity Exit from low-lower modes Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 KBIE7 0 0 KBIE6 0 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0 $001B $001C = Unimplemented Figure 20-1. KBI I/O Register Summary 20.4 I/O Pins The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 20-1. The generic pin name appear in the text that follows. Table 20-1. Pin Name Conventions KBI Generic Pin Name KBI0-KBI3 KBI4 KBI5 KBI6 KBI7 Full MCU Pin Name PTA0/KBI0-PTA3/KBI3 PTD4/KBI4/T1CLK (1) PTD5/KBI5/T2CLK (1) PTD6/KBI6/SCL (1) PTD7/KBI7/SDA (1) Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE0-KBIE3 KBIE4 KBIE5 KBIE6 KBIE7 Notes: 1. Do not enable the KBI function if the pin is used for TIM / MMIIC function. Data Sheet 408 Keyboard Interrupt Module (KBI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Functional Description 20.5 Functional Description INTERNAL BUS KBI0 VDD . KBIE0 TO PULLUP ENABLE . . D CLR Q ACKK RESET VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST CK KBI7 KEYBOARD INTERRUPT FF IMASKK MODEK KBIE7 TO PULLUP ENABLE Figure 20-2. Keyboard Interrupt Block Diagram Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables a port A or port D pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A or port D also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. * MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Data Sheet 409 Keyboard Interrupt Module (KBI) If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFDC and $FFDD. Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. * The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. Data Sheet 410 Keyboard Interrupt Module (KBI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Functional Description NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 20.5.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDR bits in data direction register. 2. Write logic 1s to the appropriate data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Data Sheet 411 Keyboard Interrupt Module (KBI) 20.6 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER) 20.6.1 Keyboard Status and Control Register * * * * Address: Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity $001B Bit 7 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 0 0 0 0 0 1 IMASKK 0 Bit 0 MODEK 0 Read: Write: Reset: 0 = Unimplemented Figure 20-3. Keyboard Status and Control Register (KBSCR) KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. Data Sheet 412 Keyboard Interrupt Module (KBI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Keyboard Interrupt Registers IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 20.6.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register individually enables or disables the PTA0/KBI0-PTA3/KBI3 and PTD4/KBI4-PTD7/KBI7 pins to operate as a keyboard interrupt pin. Address: $001C Bit 7 Read: Write: Reset: KBIE7 0 6 KBIE6 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0 Figure 20-4. Keyboard Interrupt Enable Register (KBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin NOTE: KBI5-KBI0 pin has an internal pullup device when KBIEx is set. KBI7-KBI6 pin does not have an internal pullup device. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Keyboard Interrupt Module (KBI) Data Sheet 413 Keyboard Interrupt Module (KBI) 20.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 20.7.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 20.7.2 Stop Mode The keyboard interrupt module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 20.8 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. Data Sheet 414 Keyboard Interrupt Module (KBI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 21. Computer Operating Properly (COP) 21.1 Contents 21.2 21.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 21.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 21.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 21.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 418 21.5 21.6 21.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 21.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 420 21.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration register 1 (CONFIG1). MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) Data Sheet 415 Computer Operating Properly (COP) 21.3 Functional Description Figure 21-1 shows the structure of the COP module. ICLK 12-BIT COP PRESCALER CLEAR ALL STAGES CLEAR STAGES 5-12 RESET CIRCUIT RESET STATUS REGISTER STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COP CLOCK 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) CLEAR COP COUNTER Figure 21-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 ICLK cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG1 register. With a 213 - 24 ICLK cycle overflow option, a 47-kHz ICLK gives a COP timeout period of 174ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler. NOTE: Service the COP immediately after reset and before entering or after exiting STOP Mode to guarantee the maximum time before the first COP counter overflow. Data Sheet 416 Computer Operating Properly (COP) COP TIMEOUT MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) I/O Signals A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 21.4 I/O Signals The following paragraphs describe the signals shown in Figure 21-1. 21.4.1 ICLK ICLK is the internal oscillator output signal. ICLK frequency is approximately equal to 47-kHz. See Section 24. Electrical Specifications for ICLK parameters. 21.4.2 STOP Instruction The STOP instruction clears the COP prescaler. 21.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 21.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector. 21.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 ICLK cycles after power-up. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) Data Sheet 417 Computer Operating Properly (COP) 21.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 21.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 21.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register. (See Figure 21-2 and Section 5. Configuration Registers (CONFIG).) 21.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register. Address: $001F Bit 7 Read: Write: Reset: COPRS 0 6 5 4 3 0 2 SSREC 0 1 STOP 0 Bit 0 COPD 0 LVISTOP LVIRSTD LVIPWRD 0 0 0 0 Reset by POR only. = Unimplemented Figure 21-2. Configuration Register 1 (CONFIG1) COPRS -- COP Rate Select COPRS selects the COP time-out period. Reset clears COPRS. 1 = COP time out period = 213 - 24 ICLK cycles 0 = COP time out period = 218 - 24 ICLK cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled Data Sheet 418 Computer Operating Properly (COP) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) COP Control Register 21.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 Low byte of reset vector Clear COP counter Unaffected by reset Figure 21-3. COP Control Register (COPCTL) 21.6 Interrupts The COP does not generate CPU interrupt requests. 21.7 Monitor Mode When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs. 21.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) Data Sheet 419 Computer Operating Properly (COP) 21.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 21.8.2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 21.9 COP Module During Break Mode The COP is disabled during a break interrupt when VTST is present on the RST pin. Data Sheet 420 Computer Operating Properly (COP) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 22. Low-Voltage Inhibit (LVI) 22.1 Contents 22.2 22.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 22.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 22.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .424 22.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 424 22.4.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 22.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 22.2 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 22.3 Features Features of the LVI module include: * * * Programmable LVI interrupt and reset Selectable LVI trip voltage Programmable stop mode operation MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Low-Voltage Inhibit (LVI) Data Sheet 421 Low-Voltage Inhibit (LVI) Addr. Register Name Bit 7 6 LVIIE 0 5 LVIIF 0 4 0 LVIIACK 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Read: LVIOUT Low-Voltage Inhibit Status $FE0F Register Write: (LVISR) Reset: 0 = Unimplemented Figure 22-1. LVI I/O Register Summary 22.4 Functional Description Figure 22-2 shows the structure of the LVI module. VDD STOP INSTRUCTION LVISTOP DEFAULT ENABLED FROM CONFIG1 FROM CONFIG1 LVIRSTD LVIPWRD FROM CONFIG1 LOW VDD DETECTOR VDD > VTRIPR = 0 VDD VTRIPF = 1 FROM LVISR LVI RESET LVIIE LVISEL[1:0] FROM CONFIG2 EDGE DETECT LATCH CLR LVI INTERRUPT REQUEST LVIOUT TO LVISR LVIIACK FROM LVISR LVIIF TO LVISR Figure 22-2. LVI Module Block Diagram The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Data Sheet 422 Low-Voltage Inhibit (LVI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Low-Voltage Inhibit (LVI) Functional Description The LVI trip point selection bits, LVISEL[1:0], select the trip point voltage, VTRIPF, to be configured for 5V or 3V operation. The actual trip points are shown in Section 24. Electrical Specifications. Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0). NOTE: After a power-on reset (POR) the LVI's default mode of operation is 3V. If a 5V system is used, the user must modified the LVISEL[1:0] bits to raise the trip point to 5V operation. Note that this must be done after every power-on reset since the default will revert back to 3V mode after each power-on reset. If the VDD supply is below the 3V mode trip voltage when POR is released, the MCU will immediately go into reset. The LVI in this case will hold the MCU in reset until either VDD goes above the rising 3V trip point, VTRIPR, which will release reset or VDD decreases to approximately 0V which will re-trigger the power-on reset. LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the configuration registers. See Section 5. Configuration Registers (CONFIG) for details of the LVI's configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 9.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIACK bits in the LVISR control LVI interrupt functions. An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Low-Voltage Inhibit (LVI) Data Sheet 423 Low-Voltage Inhibit (LVI) 22.4.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit, or by setting the LVI interrupt enable bit, LVIIE, to enable interrupt requests. In the configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes state (toggles). When LVIF is set, a CPU interrupt request is generated if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF bit can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit, LVIIACK. 22.4.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register 1 (CONFIG1), the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI reset has a higher priority over LVI interrupt. In this case, when VDD falls below the VTRIPF level, an LVI reset will occur, and the LVIIE bit will be cleared. 22.4.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. Data Sheet 424 Low-Voltage Inhibit (LVI) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Low-Voltage Inhibit (LVI) LVI Status Register 22.4.4 LVI Trip Selection The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select whether the LVI is configured for 5V or 3 V operation. (See Section 5. Configuration Registers (CONFIG).) NOTE: The MCU is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5V] or VTRIPF [3V]) may be lower than this. (See Section 24. Electrical Specifications for the actual trip point voltages.) 22.5 LVI Status Register The LVI status register (LVISR) controls LVI interrupt functions and indicates if the VDD voltage was detected below the VTRIPF level. Address: $FE0F Bit 7 Read: Write: Reset: 0 LVIOUT 6 LVIIE 0 5 LVIIF 4 0 LVIIACK 0 0 0 0 0 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Table 22-1. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage (see Table 22-2). Reset clears the LVIOUT bit. Table 22-2. LVIOUT Bit Indication VDD VDD > VTRIPR VDD < VTRIPF VTRIPF < VDD < VTRIPR LVIOUT 0 1 Previous value MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Low-Voltage Inhibit (LVI) Data Sheet 425 Low-Voltage Inhibit (LVI) LVIIE -- LVI Interrupt Enable Bit This read/write bit enables the LVIIF bit to generate CPU interrupt requests. Reset clears the LVIIE bit. 1 = LVIIF can generate CPU interrupt requests 0 = LVIIF cannot generate CPU interrupt requests LVIIF -- LVI Interrupt Flag This clearable, read-only flag is set whenever the LVIOUT bit toggles. Reset clears the LVIIF bit. 1 = LVIOUT has toggled 0 = LVIOUT has not toggled LVIIACK -- LVI Interrupt Acknowledge Bit Writing a logic 1 to this write-only bit clears the LVI interrupt flag, LVIIF. LVIIACK always reads as logic 0. 1 = Clears LVIIF bit 0 = No effect 22.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 22.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets or interrupts, the LVI module can generate a reset or an interrupt and bring the MCU out of wait mode. 22.6.2 Stop Mode If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode. If enabled to generate resets or interrupts, the LVI module can generate a reset or an interrupt and bring the MCU out of stop mode. NOTE: If enabled to generate both resets and interrupts, there will be no LVI interrupts, as resets have a higher priority. MC68HC908LJ24/LK24 -- Rev. 2.1 Low-Voltage Inhibit (LVI) Freescale Semiconductor Data Sheet 426 Data Sheet -- MC68HC908LJ24 Section 23. Break Module (BRK) 23.1 Contents 23.2 23.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 23.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 430 23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .430 23.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . . 430 23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 430 23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 431 23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 432 23.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 432 23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 434 23.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Data Sheet 427 Break Module (BRK) 23.3 Features Features of the break module include: * * * * Accessible input/output (I/O) registers during the break interrupt CPU-generated break interrupts Software-generated break interrupts COP disabling during break interrupts 23.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic 1 to the BRKA bit in the break status and control register. When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 23-1 shows the structure of the break module. Data Sheet 428 Break Module (BRK) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Functional Description IAB15-IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15-IAB0 CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK IAB7-IAB0 Figure 23-1. Break Module Block Diagram Addr. Register Name Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note 0 Bit 0 R Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: $FE03 Read: SIM Break Flag Control Register Write: (SBFCR) Reset: Read: Break Address Register High Write: (BRKH) Reset: Read: Break Address Register Low Write: (BRKL) Reset: BCFE 0 Bit 15 0 Bit 7 0 BRKE 0 R R R R R R R $FE0C 14 0 6 0 BRKA 0 13 0 5 0 0 0 12 0 4 0 0 0 11 0 3 0 0 0 R 10 0 2 0 0 0 = Reserved 9 0 1 0 0 0 Bit 8 0 Bit 0 0 0 0 $FE0D Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Note: Writing a logic 0 clears SBSW. = Unimplemented Figure 23-2. Break Module I/O Register Summary MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Data Sheet 429 Break Module (BRK) 23.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 23.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 23.4.3 TIM1 and TIM2 During Break Interrupts A break interrupt stops the timer counters. 23.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin. 23.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 23.5.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see Section 9. System Integration Module (SIM)). Clear the SBSW bit by writing logic 0 to it. Data Sheet 430 Break Module (BRK) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Break Module Registers 23.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 23.6 Break Module Registers These registers control and monitor operation of the break module: * * * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) SIM break status register (SBSR) SIM break flag control register (SBFCR) 23.6.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0E Bit 7 Read: Write: Reset: BRKE 0 6 BRKA 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 = Unimplemented Figure 23-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Data Sheet 431 Break Module (BRK) BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 23.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE0C Bit 7 Read: Write: Reset: Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0 Figure 23-4. Break Address Register High (BRKH) Address: $FE0D Bit 7 Read: Write: Reset: Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 Figure 23-5. Break Address Register Low (BRKL) 23.6.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. Data Sheet 432 Break Module (BRK) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Break Module Registers Address: $FE00 Bit 7 6 R 0 5 R 0 R 4 R 0 = Reserved 3 R 0 2 R 0 1 SBSW Note 0 Bit 0 R 0 Read: Write: Reset: R 0 Note: Writing a logic 0 clears SBSW. Figure 23-6. SIM Break Status Register (SBSR) SBSW -- Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it. The following code is an example. ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE LOBYTE ; EQU EQU 5 6 If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Break Module (BRK) Data Sheet 433 Break Module (BRK) 23.6.4 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R Figure 23-7. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 434 Break Module (BRK) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 24. Electrical Specifications 24.1 Contents 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 437 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 438 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 439 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.10 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 441 24.11 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 442 24.12 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 443 24.13 3.3V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .444 24.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 445 24.15 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 445 24.16 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 24.17 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 24.18 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 450 24.2 Introduction This section contains electrical and timing specifications. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 435 Electrical Specifications 24.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to DC Electrical Characteristics for guaranteed operating conditions. Table 24-1. Absolute Maximum Ratings Characteristic(1) Supply voltage Input voltage All pins (except IRQ) IRQ pin Maximum current per pin excluding VDD and VSS Maximum current out of VSS Maximum current into VDD Storage temperature Notes: 1. Voltages referenced to VSS. Symbol VDD VIN Value -0.3 to +6.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to 8.5 25 100 100 -55 to +150 Unit V V I IMVSS IMVDD TSTG mA mA mA C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.) Data Sheet 436 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Functional Operating Range 24.4 Functional Operating Range Table 24-2. Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value - 40 to +85 3.3 10% 5 10% Unit C V 24.5 Thermal Characteristics Table 24-3. Thermal Characteristics Characteristic Thermal resistance 64-pin LQFP 64-pin QFP 80-pin LQFP 80-pin QFP I/O pin power dissipation Power dissipation(1) Symbol Value 72 67 85 75 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) Unit JA C/W PI/O PD W W Constant(2) Average junction temperature K TJ W/C C Notes: 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 437 Electrical Specifications 24.6 5V DC Electrical Characteristics Table 24-4. 5V DC Electrical Characteristics Characteristic(1) Output high voltage (ILOAD = -2.0 mA) All ports Output low voltage (ILOAD = 1.6mA) All ports (ILOAD = 15.0 mA) PTB0-PTB5, PTC0-PTC7, PTE0-PTE7, PTF0-PTF7 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current Run(3), fOP = 8 MHz with all modules on with ADC on with ADC off Wait(4), fOP = 8 MHz (all modules off) Stop, fOP = 8 kHz with OSC, RTC, LCD(6), LVI on with OSC, RTC, LCD(6) on with OSC, RTC on all modules off Digital I/O ports Hi-Z leakage current All ports, RST Input current IRQ Capacitance Ports (as input or output) POR re-arm voltage(7) POR rise-time ramp rate(8) Monitor mode entry voltage (at IRQ pin) Pullup resistors(9) PTA0-PTA3 and PTD4-PTD7 as KBI0-KBI7 RST, IRQ Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage IIL IIN COUT CIN VPOR RPOR VTST RPU1 RPU2 VTRIPF VTRIPR (5) Symbol VOH Min VDD -0.8 Typ(2) -- Max -- Unit V VOL -- -- 0.4 V VIH VIL 0.7 x VDD VSS -- -- VDD 0.3 x VDD V V -- -- -- IDD -- -- -- -- -- -- -- -- -- 0 0.035 1.5 x VDD 21 21 3.6 3.7 15 13 10.5 5 300 20 7 -- -- -- -- -- -- -- -- 30 30 -- -- 20 18 14 8 400 30 12 1 10 1 12 8 100 -- 8 39 39 4.6 4.7 mA mA mA mA A A A A A A pF mV V/ms V k k V V Data Sheet 438 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications 3.3V DC Electrical Characteristics Notes: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. The 8kHz clock is from a 32kHz external square wave clock input at OSC1, for the driving the RTC. Due to loading effects, the IDD values will be larger when a 32kHz crystal circuit is connected. 6. LCD driver configured for low current mode. 7. Maximum is highest voltage that POR is guaranteed. 8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 9. RPU1 and RPU2 are measured at VDD = 5.0V 24.7 3.3V DC Electrical Characteristics Table 24-5. 3.3V DC Electrical Characteristics Characteristic(1) Output high voltage (ILOAD = -1.0 mA) All ports Output low voltage (ILOAD = 0.8mA) All ports (ILOAD = 10.0 mA) PTB0-PTB5, PTC0-PTC7, PTE0-PTE7, PTF0-PTF7 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current Run(3), fOP = 4 MHz with all modules on with ADC on with ADC off Wait(4), fOP = 4 MHz (all modules off) Stop, fOP = 8 kHz(5) with OSC, RTC, LCD(6), LVI on with OSC, RTC, LCD(6) on with OSC, RTC on all modules off Digital I/O ports Hi-Z leakage current All ports, RST Input current IRQ IIL IIN IDD -- -- -- -- -- -- -- -- -- -- 5.5 4.5 3 1.5 180 15 2.5 -- -- -- 8 6 5 2.5 250 20 4 1 10 1 mA mA mA mA A A A A A A Symbol VOH Min VDD -0.4 Typ(2) -- Max -- Unit V VOL -- -- 0.4 V VIH VIL 0.7 x VDD VSS -- -- VDD 0.3 x VDD V V MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 439 Electrical Specifications Table 24-5. 3.3V DC Electrical Characteristics Characteristic(1) Capacitance Ports (as input or output) POR re-arm voltage(7) POR rise-time ramp rate(8) Monitor mode entry voltage (at IRQ pin) Pullup resistors(9) PTA0-PTA3 and PTD4-PTD7 as KBI0-KBI7 RST, IRQ Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Symbol COUT CIN VPOR RPOR VHI RPU1 RPU2 VTRIPF VTRIPR Min -- -- 0 0.02 1.5 x VDD 21 21 2.1 2.2 Typ(2) -- -- -- -- -- 30 30 -- -- Max 12 8 100 -- 8 39 39 2.8 2.9 Unit pF mV V/ms V k k V V Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. The 8kHz clock is from a 32kHz external square wave clock input at OSC1, for the driving the RTC. Due to loading effects, the IDD values will be larger when a 32kHz crystal circuit is connected. 6. LCD driver configured for low current mode. 7. Maximum is highest voltage that POR is guaranteed. 8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 9. RPU1 and RPU2 are measured at VDD = 3.3V. 24.8 5V Control Timing Table 24-6. 5V Control Timing Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 750 Max 8 -- Unit MHz ns Notes: 1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. Data Sheet 440 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications 3.3V Control Timing 24.9 3.3V Control Timing Table 24-7. 3.3V Control Timing Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 1.5 Max 4 -- Unit MHz s Notes: 1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. 24.10 5V Oscillator Characteristics Table 24-8. 5V Oscillator Specifications Characteristic Internal oscillator clock frequency External reference clock to OSC1(2) Crystal reference frequency(3) Crystal load capacitance(4) Crystal fixed capacitance Crystal tuning capacitance Feedback bias resistor Series resistor(5) Symbol fICLK fOSC fXCLK CL C1 C2 RB RS dc -- -- -- -- -- -- Min Typ 50k(1) -- 32.768k -- 2 x CL (27p) 2 x CL (33p) 20M 100k 20M 4.9152M -- -- -- -- -- F F Max Unit Hz Hz Hz Notes: 1. Typical value reflect average measurements at midpoint of voltage range, 25 xC only. See Figure 24-1 for plot. 2. No more than 10% duty cycle deviation from 50%. 3. Fundamental mode crystals only. 4. Consult crystal manufacturer's data. 5. Not Required for high frequency crystals. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 441 Electrical Specifications 24.11 3.3V Oscillator Characteristics Table 24-9. 3.3V Oscillator Specifications Characteristic Internal oscillator clock frequency External reference clock to OSC1(2) Crystal reference frequency(3) Crystal load capacitance(4) Crystal fixed capacitance Crystal tuning capacitance Feedback bias resistor Series resistor(5) Symbol fICLK fOSC fXCLK CL C1 C2 RB RS dc -- -- -- -- -- -- Min Typ 47k(1) -- 32.768k -- 2 x CL (27p) 2 x CL (33p) 20M 100k 16M 4.9152M -- -- -- -- -- F F Max Unit Hz Hz Hz Notes: 1. Typical value reflect average measurements at midpoint of voltage range, 25 xC only. See Figure 24-1 for plot. 2. No more than 10% duty cycle deviation from 50%. 3. Fundamental mode crystals only. 4. Consult crystal manufacturer's data. 5. Not Required for high frequency crystals. Internal OSC frequency, fICLK (kHz) 65 60 55 50 45 40 35 2 3 4 5 Supply Voltage, VDD (V) 6 +85C +25C -40C Figure 24-1. Typical Internal Oscillator Frequency Data Sheet 442 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications 5V ADC Electrical Characteristics 24.12 5V ADC Electrical Characteristics Table 24-10. 5V ADC Electrical Characteristics Characteristic Supply voltage Symbol VDDA VADIN BAD AAD fADIC RAD VREFH VREFL tADC tADS MAD ZADI FADI CADI RADI IVREF 000 3FC -- 20M -- Min 4.5 Max 5.5 VDDA 10 1.5 2M VREFH VDDA + 0.1 -- 17 -- Guaranteed 001 3FF 20 -- 1.6 HEX HEX pF mA Not tested. VADIN = VREFL VADIN = VREFH Not tested. Unit V Notes VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. VADIN VDDA Input range Resolution Absolute accuracy ADC internal clock Conversion range ADC voltage reference high ADC voltage reference low Conversion time Sample time Monotonically Zero input reading Full-scale reading Input capacitance Input impedance VREFH/VREFL 0 10 -- 32 k VREFL -- VSSA - 0.1 16 5 V bits LSB Hz V V V tADIC cycles tADIC cycles Includes quantization. 0.5 LSB = 1 ADC count. tADIC = 1/fADIC VSSA is tied to VSS internally. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 443 Electrical Specifications 24.13 3.3V ADC Electrical Characteristics Table 24-11. 3.3V ADC Electrical Characteristics Characteristic Supply voltage Symbol VDDA VADIN BAD AAD fADIC RAD VREFH VREFL tADC tADS MAD ZADI FADI CADI RADI IVREF 000 3FC -- 20M -- Min 3.0 Max 3.6 VDDA 10 1.5 2M VREFH VDDA + 0.1 -- 17 -- Guaranteed 001 3FF 20 -- 1.6 HEX HEX pF mA VADIN = VREFL VADIN = VREFH Not tested. Measured at 5V Not tested. Unit V Notes VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. VADIN VDDA Input range Resolution Absolute accuracy ADC internal clock Conversion range ADC voltage reference high ADC voltage reference low Conversion time Sample time Monotonically Zero input reading Full-scale reading Input capacitance Input impedance VREFH/VREFL 0 10 -- 32 k VREFL -- VSSA - 0.1 16 5 V bits LSB Hz V V V tADIC cycles tADIC cycles Includes quantization. 0.5 LSB = 1 ADC count. tADIC = 1/fADIC VSSA is tied to VSS internally. Data Sheet 444 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Timer Interface Module Characteristics 24.14 Timer Interface Module Characteristics Table 24-12. Timer Interface Module Characteristics Characteristic Input capture pulse width Symbol tTIH, tTIL Min 1 Max -- Unit tCYC 24.15 CGM Electrical Specifications Table 24-13. CGM Electrical Specifications Characteristic Reference frequency Range nominal multiplies VCO center-of-range frequency VCO range linear range multiplier VCO power-of-two-range multiplier VCO multiply factor VCO prescale multiplier Reference divider factor VCO operating frequency Manual acquisition time Automatic lock time (1) Symbol fRDV fNOM fVRS L 2E N 2P R fVCLK tLOCK tLOCK fJ Min 30 -- 38.4k 1 1 1 1 1 38.4k -- -- Typ 32.768 38.4 -- -- -- -- -- 1 -- -- -- Max 100 -- 40.0M 255 4 4095 8 15 40.0M 50 50 fRCLK x 0.025% x 2P N/4 Unit kHz kHz Hz Hz ms ms PLL jitter 0 -- Hz Notes: 1. Deviation of average bus frequency over 2ms. N = VCO multiplier. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 445 Electrical Specifications 24.16 5V SPI Characteristics Table 24-14. 5V SPI Characteristics Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S) fOP/128 dc 2 1 1 1 tCYC -25 1/2 tCYC -25 tCYC -25 1/2 tCYC -25 30 30 30 30 0 0 -- -- -- 0 0 fOP/2 fOP 128 -- -- -- 64 tCYC -- 64 tCYC -- -- -- -- -- 40 40 40 50 50 -- -- MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7 8 9 10 11 Notes: 1. Numbers refer to dimensions in Figure 24-2 and Figure 24-3. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins Data Sheet 446 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications 3.3V SPI Characteristics 24.17 3.3V SPI Characteristics Table 24-15. 3.3V SPI Characteristics Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(s) tLag(s) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S) fOP/128 dc 2 1 1 1 tCYC -35 1/2 tCYC -35 tCYC -35 1/2 tCYC -35 40 40 40 40 0 0 -- -- -- 0 0 fOP/2 fOP 128 -- -- -- 64 tCYC -- 64 tCYC -- -- -- -- -- 50 50 50 60 60 -- -- MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7 8 9 10 11 Notes: 1. Numbers refer to dimensions in Figure 24-2 and Figure 24-3. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 447 Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE 5 4 5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT SPSCK OUTPUT CPOL = 1 NOTE MISO INPUT MSB IN 11 BITS 6-1 MOSI OUTPUT MASTER MSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin. a) SPI Master Timing (CPHA = 0) SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 5 4 5 4 6 7 LSB IN 10 BITS 6-1 MASTER LSB OUT NOTE SPSCK OUTPUT CPOL = 1 NOTE MISO INPUT 10 MOSI OUTPUT MSB IN 11 MASTER MSB OUT BITS 6-1 Note: This last clock edge is generated internally, but is not seen at the SPSCK pin. b) SPI Master Timing (CPHA = 1) Figure 24-2. SPI Master Timing Data Sheet 448 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications 3.3V SPI Characteristics SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 5 4 3 Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3 Note: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 24-3. SPI Slave Timing MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Electrical Specifications Data Sheet 449 Electrical Specifications 24.18 FLASH Memory Characteristics Table 24-16. FLASH Memory Electrical Characteristics Characteristic RAM data retention voltage Number of rows per page Number of bytes per page Read bus clock frequency Page erase time Mass erase time PGM/ERASE to HVEN setup time High-voltage hold time High-voltage hold time (mass erase) Program hold time Program time Address/data setup time Address/data hold time Recovery time Cumulative HV period Row erase endurance(6) Row program endurance(7) Data retention time(8) fread(1) terase(2) tmerase(3) tnvs tnvh tnvhl tpgs tprog tads tadh trcv(4) thv(5) -- -- -- 32k 1 4 10 5 100 5 30 -- -- 1 -- 10k 10k 10 Symbol VRDR Min. 1.3 2 128 8M -- -- -- -- -- -- 40 30 30 -- 25 -- -- -- Max. -- Unit V Rows Bytes Hz ms ms s s s s s ns ns s ms Cycles Cycles Years Notes: 1. fread is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than terase (Min.), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tmerase (Min.), there is no erase-disturb, but is reduces the endurance of the FLASH memory. 4. It is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. thv is the cumulative high voltage programming time to the same row before next erase, and the same address can not be programmed twice before next erase. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase/program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase/program cycle. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. Data Sheet 450 Electrical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 25. Mechanical Specifications 25.1 Contents 25.2 25.3 25.4 25.5 25.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 64-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 452 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 453 80-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 454 80-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 455 25.2 Introduction This section gives the dimensions for: * * * * 64-pin low-profile quad flat pack (case no. 840F) 64-pin quad flat pack (case no. 840B) 80-pin low-profile quad flat pack (case no. 917) 80-pin quad flat pack (case no. 841B) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Mechanical Specifications Data Sheet 451 Mechanical Specifications 25.3 64-Pin Low-Profile Quad Flat Pack (LQFP) 4X 4X 16 TIPS 0.2 H A-B D 64 1 49 0.2 C A-B D A2 0.05 (S) S 48 1 A B E1 3X 2X R R1 0.25 GAGE PLANE E A1 (L2) L (L) VIEW AA NOTES: 1. ALL DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.35. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07. DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 L2 R1 S 1 2 3 MILLIMETERS MIN MAX -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.17 0.23 0.09 0.20 0.09 0.16 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC 0.45 0.75 1.00 REF 0.50 REF 0.10 0.20 0.20 REF 0 7 -- 0 12 REF 12 REF VIEW Y 16 17 32 33 E1/2 E/2 D D1/2 D/2 D1 D H A 4X (2) 0.08 C C SEATING PLANE 4X (3) VIEW AA BASE METAL b1 X X=A, B OR D c c1 C L AB AB VIEW Y e/2 60X PLATING b 0.08 M e C A-B D SECTION AB-AB ROTATED 90 CLOCKWISE Figure 25-1. 64-Pin Low-Profile Quad Flat Pack (Case No. 840F) Data Sheet 452 Mechanical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Mechanical Specifications 64-Pin Quad Flat Pack (QFP) 25.4 64-Pin Quad Flat Pack (QFP) L 48 49 33 32 S S D D B B P S -A- L -B- B H A-B 0.05 (0.002) A-B V M 0.20 (0.008) 0.20 (0.008) M C A-B S -A-, -B-, -D- DETAIL A DETAIL A 64 17 1 F 16 -D- A 0.20 (0.008) M H A-B S D S J N 0.05 (0.002) A-B S 0.20 (0.008) M C A-B E S D M S D DETAIL C 0.20 (0.008) M BASE METAL C A-B S D S C -C- SEATING PLANE -H- H M G DATUM PLANE SECTION B-B VIEW ROTATED 90 0.10 (0.004) U T R -H- DATUM PLANE Q K W X DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.30 0.45 2.00 2.40 0.30 0.40 0.80 BSC -- 0.25 0.13 0.23 0.65 0.95 12.00 REF 5 10 0.13 0.17 0.40 BSC 0 7 0.13 0.30 16.95 17.45 0.13 -- 0 -- 16.95 17.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.547 0.555 0.547 0.555 0.085 0.096 0.012 0.018 0.079 0.094 0.012 0.016 0.031 BSC -- 0.010 0.005 0.009 0.026 0.037 0.472 REF 5 10 0.005 0.007 0.016 BSC 0 7 0.005 0.012 0.667 0.687 0.005 -- 0 -- 0.667 0.687 0.014 0.018 0.063 REF Figure 25-2. 64-Pin Quad Flat Pack (Case No. 840B) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Mechanical Specifications Data Sheet 453 Mechanical Specifications 25.5 80-Pin Low-Profile Quad Flat Pack (LQFP) B D D/2 D1 D1/2 PIN 1 IDEx 1 80 61 60 B VIEW Y e/2 X VIEW Y 3 PLACES X=A, B, or D E/2 b1 PLATING E E1 A B E1/2 20 21 40 41 c c1 b 0.08 M C A-B D SECTION B-B 80 PLACES ROTATED 90 CLOCKWISE BASE METAL D 4X 4X 0.200 H A-B D 0.200 C A-B D A2 A A1 8X 2 VIEW P H 0.1 C 76X e C SEATING PLANE NOTES: 1. ALL DIMENSIONS AND TOLERANCES TO CONFORM TO ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.35. MILLIMETERS MIN MAX -- 1.60 0.05 0.15 1.35 1.45 14.00 BSC 12.00 BSC 14.00 BSC 12.00 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 REF 0.20 REF 0.17 REF 0.17 0.27 0.17 0.23 0.12 0.20 0.12 0.16 0.50 BSC 0 7 0 -- 10 14 S 1 R (R1) R (R2) GAGE PLANE (L2) 0.25 (L1) VIEW P L DIM A A1 A2 D D1 E E1 L L1 L2 R1 R2 S b b1 c c1 e 1 2 Figure 25-3. 80-Pin Low-Profile Quad Flat Pack (Case No. 917) Data Sheet 454 Mechanical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Mechanical Specifications 80-Pin Quad Flat Pack (QFP) 25.6 80-Pin Quad Flat Pack (QFP) L 60 61 41 40 S S B B P D S H A-B -A- L B V 0.05 D M M C A-B -B- S D 0.20 0.20 -A-,-B-,-D- DETAIL A DEATIL A 80 1 20 21 -D- 0.20 M F A H A-B S S D S 0.05 A-B J S N 0.20 E C -C- SEATING PLANE M C A-B D S M DETAIL C -H- H G DATUM PLANE D 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 0.10 M U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC -- 0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 -- 0 -- 16.95 17.45 0.35 0.45 1.6 REF Figure 25-4. 80-Pin Quad Flat Pack (Case No. 841B) MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Mechanical Specifications Data Sheet 455 Mechanical Specifications Data Sheet 456 Mechanical Specifications MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Section 26. Ordering Information 26.1 Contents 26.2 26.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 26.2 Introduction This section contains ordering numbers for the MC68HC908LJ24. 26.3 MC Order Numbers Table 26-1. MC Order Numbers MC Order Number MC68HC908LJ24CPB MC68HC908LJ24CFU MC68HC908LJ24CPK MC68HC908LJ24CFQ Package 64-pin LQFP 64-pin QFP 80-pin LQFP 80-pin QFP Operating Temperature Range -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Ordering Information Data Sheet 457 Ordering Information Data Sheet 458 Ordering Information MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet -- MC68HC908LJ24 Appendix A. MC68HC908LK24 A.1 Contents A.2 A.3 A.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 A.5.1 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 461 A.5.2 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 461 A.5.3 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . .462 A.5.4 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . 462 A.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 A.2 Introduction The MC68HC908LK24 is a MC68HC908LJ24 with a low-power oscillator that supports a 32.768kHz crystal only. The entire data book apply to the MC68HC908LK24 device, with exceptions outlined in this appendix. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet 459 A.3 Oscillator The low-power oscillator supports a reference frequency of 32.768kHz only; either from a crystal oscillator circuit (Figure A-1) or a direct clock input to the OSC1 pin. MCU OSC1 RB OSC2 RS 32.768kHz C1 X1 C2 Figure A-1. MC68HC908LK24 Crystal Oscillator Connection A.4 Low-Voltage Inhibit The LVIPWRD bit in CONFIG1 register is logic 1 after any reset. Address: $001F Bit 7 Read: Write: MC68HC908LK24 MC68HC908LJ24 Reset by POR only. Reset: Reset: COPRS 0 0 6 5 4 3 0 2 SSREC 0 0 1 STOP 0 0 Bit 0 COPD 0 0 LVISTOP LVIRSTD LVIPWRD 0 0 0 0 1 0 0 0 = Unimplemented Figure A-2. MC68HC908LK24 Configuration Register 1 (CONFIG1) LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled Data Sheet 460 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor A.5 Electrical Specifications Electrical specifications for the MC68HC908LJ24 apply to the MC68HC908LK24, except for the parameters indicated below. A.5.1 5V DC Electrical Characteristics Table A-1. 5V DC Electrical Characteristics Characteristic(1) VDD supply current Stop, fOP = 8 kHz(3) with OSC, RTC on Low-voltage inhibit, trip rising voltage LVI reset disabled (LVIRSTD = 1) LVI reset enabled (LVIRSTD = 0) IDD -- VTRIPR 3.7 3.62 5.5 -- -- 7.5 4.7 4.62 A V V Symbol Min Typ(2) Max Unit Notes: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. The 8kHz clock is from a 32kHz external square wave clock input at OSC1, for the driving the RTC. Due to loading effects, the IDD values will be larger when a 32kHz crystal circuit is connected. A.5.2 3.3V DC Electrical Characteristics Table A-2. 3.3V DC Electrical Characteristics Characteristic(1) Low-voltage inhibit, trip rising voltage LVI disabled (LVIRSTD = 1) LVI enabled (LVIRSTD = 0) Symbol VTRIPR Min 2.2 2.12 Typ(2) -- -- Max 2.9 2.82 Unit V V Notes: 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor Data Sheet 461 A.5.3 5V Oscillator Characteristics Table A-3. 5V Oscillator Specifications Characteristic External reference clock to OSC1(1) Crystal reference frequency(2) Notes: 1. No more than 10% duty cycle deviation from 50%. 2. Fundamental mode crystals only. Symbol fOSC fXCLK Min dc -- Typ 32.768k 32.768k Max -- -- Unit Hz Hz A.5.4 3.3V Oscillator Characteristics Table A-4. 3.3V Oscillator Specifications Characteristic External reference clock to OSC1(1) Crystal reference frequency(2) Notes: 1. No more than 10% duty cycle deviation from 50%. 2. Fundamental mode crystals only. Symbol fOSC fXCLK Min dc -- Typ 32.768k 32.768k Max -- -- Unit Hz Hz A.6 MC Order Numbers Table A-5 shows the ordering numbers for the MC68HC908LK24. Table A-5. MC68HC908LK24 Order Numbers MC Order Number MC68HC908LK24CPB MC68HC908LK24CFU MC68HC908LK24CPK MC68HC908LK24CFQ Package 64-pin LQFP 64-pin QFP 80-pin LQFP 80-pin QFP Operating Temperature Range -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C Data Sheet 462 MC68HC908LJ24/LK24 -- Rev. 2.1 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Rev. 2.1 MC68HC908LJ24/D August 16, 2005 RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The ARM POWERED logo is a registered trademark of ARM Limited. ARM7TDMI-S is a trademark of ARM Limited. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The Bluetooth trademarks are owned by their proprietor and used by Freescale Semiconductor, Inc. under license. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. |
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